Yiran Chen

Orcid: 0000-0002-1486-8412

Affiliations:
  • Duke University, Department of Electrical and Computer Engineering, Durham, NC, USA
  • University of Pittsburgh, Department of Electrical and Computer Engineering, Pittsburgh, PA, USA (since 2010)
  • Seagate Technologies, Inc., Bloomington, MN, USA (2007 - 2010)
  • Synopsys Inc., Mountain View, CA, USA (2005 - 2007)
  • Purdue University, West Lafayette, IN, USA (PhD 2005)


According to our database1, Yiran Chen authored at least 570 papers between 2002 and 2024.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2020, "For contributions to to nonvolatile memory technologies".

IEEE Fellow

IEEE Fellow 2018, "For contributions to spintronic memory".

Timeline

Legend:

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Article 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
Designing Efficient Bit-Level Sparsity-Tolerant Memristive Networks.
IEEE Trans. Neural Networks Learn. Syst., September, 2024

Lithography Hotspot Detection Based on Heterogeneous Federated Learning With Local Adaptation and Feature Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

NDRec: A Near-Data Processing System for Training Large-Scale Recommendation Models.
IEEE Trans. Computers, May, 2024

Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Toward Fully Automated Machine Learning for Routability Estimator Development.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

Efficient Low-Bit Neural Network With Memristor-Based Reconfigurable Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A memristive all-inclusive hypernetwork for parallel analog deployment of full search space architectures.
Neural Networks, 2024

Federated Large Language Models: Current Progress and Future Directions.
CoRR, 2024

FedProphet: Memory-Efficient Federated Adversarial Training via Theoretic-Robustness and Low-Inconsistency Cascade Learning.
CoRR, 2024

MLLM-FL: Multimodal Large Language Model Assisted Federated Learning on Heterogeneous and Long-tailed Data.
CoRR, 2024

Dataset Distillation from First Principles: Integrating Core Information Extraction and Purposeful Learning.
CoRR, 2024

PatternPaint: Generating Layout Patterns Using Generative AI and Inpainting Techniques.
CoRR, 2024

Criticality Leveraged Adversarial Training (CLAT) for Boosted Performance via Parameter Efficiency.
CoRR, 2024

LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits.
CoRR, 2024

MonoSparse-CAM: Harnessing Monotonicity and Sparsity for Enhanced Tree Model Processing on CAMs.
CoRR, 2024

Decentralized Multi-Party Multi-Network AI for Global Deployment of 6G Wireless Systems.
CoRR, 2024

ARTIST: Improving the Generation of Text-rich Images by Disentanglement.
CoRR, 2024

Can Dense Connectivity Benefit Outlier Detection? An Odyssey with NAS.
CoRR, 2024

Knowledge Graph Tuning: Real-time Large Language Model Personalization based on Human Feedback.
CoRR, 2024

OSR-ViT: A Simple and Modular Framework for Open-Set Object Detection and Discovery.
CoRR, 2024

Advancing Real-time Pandemic Forecasting Using Large Language Models: A COVID-19 Case Study.
CoRR, 2024

Peeking Behind the Curtains of Residual Learning.
CoRR, 2024

Group Distributionally Robust Dataset Distillation with Risk Minimization.
CoRR, 2024

Qplacer: Frequency-Aware Component Placement for Superconducting Quantum Computers.
CoRR, 2024

Athena - The NSF AI Institute for Edge Computing.
AI Mag., 2024

Efficient, Direct, and Restricted Black-Box Graph Evasion Attacks to Any-Layer Graph Neural Networks via Influence Function.
Proceedings of the 17th ACM International Conference on Web Search and Data Mining, 2024

Tunable Hybrid Proposal Networks for the Open World.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024

ModelGuard: Information-Theoretic Defense Against Model Extraction Attacks.
Proceedings of the 33rd USENIX Security Symposium, 2024

SiDA: Sparsity-Inspired Data-Aware Serving for Efficient and Scalable Large Mixture-of-Experts Models.
Proceedings of the Seventh Annual Conference on Machine Learning and Systems, 2024

Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Mitigating Bias of Deep Neural Networks for Trustworthy Traffic Perception in Autonomous Systems.
Proceedings of the IEEE Intelligent Vehicles Symposium, 2024

Cost-effective Vehicle Recognition System in Challenging Environment Empowered by Micro-Pulse LiDAR and Edge AI.
Proceedings of the IEEE Intelligent Vehicles Symposium, 2024

Embracing Privacy, Robustness, and Efficiency with Trustworthy Federated Learning on Edge Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Hybrid Digital/Analog Memristor-based Computing Architecture for Sparse Deep Learning Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

NDSEARCH: Accelerating Graph-Traversal-Based Approximate Nearest Neighbor Search through Near Data Processing.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits.
Proceedings of the Forty-first International Conference on Machine Learning, 2024

FedBPT: Efficient Federated Black-box Prompt Tuning for Large Language Models.
Proceedings of the Forty-first International Conference on Machine Learning, 2024

SD-NAE: Generating Natural Adversarial Examples with Stable Diffusion.
Proceedings of the Second Tiny Papers Track at ICLR 2024, 2024

Towards Building The Federatedgpt: Federated Instruction Tuning.
Proceedings of the IEEE International Conference on Acoustics, 2024

Processing-in-Memory Designs Based on Emerging Technology for Efficient Machine Learning Acceleration.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Unlocking the Potential of Federated Learning: The Symphony of Dataset Distillation via Deep Generative Latents.
Proceedings of the Computer Vision - ECCV 2024, 2024

Improving the Efficiency of In-Memory-Computing Macro with a Hybrid Analog-Digital Computing Mode for Lossless Neural Network Inference.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Efficient Memory Integration: MRAM-SRAM Hybrid Accelerator for Sparse On-Device Learning.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

CSCO: Connectivity Search of Convolutional Operators.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024

Efficient Dataset Distillation via Minimax Diffusion.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024

A Quantized Parsimonious CNN Model for Sleep Polysomnogram Data Streams.
Proceedings of the IEEE/ACM Conference on Connected Health: Applications, 2024

A Deep-Learning-Based Multi-modal ECG and PCG Processing Framework for Label Efficient Heart Sound Segmentation.
Proceedings of the IEEE/ACM Conference on Connected Health: Applications, 2024

Advancing Federated Learning by Addressing Data and System Heterogeneity.
Proceedings of the AAAI 2024 Spring Symposium Series, 2024

2023
EMS-i: An Efficient Memory System Design with Specialized Caching Mechanism for Recommendation Inference.
ACM Trans. Embed. Comput. Syst., October, 2023

SpikeSen: Low-Latency In-Sensor-Intelligence Design With Neuromorphic Spiking Neurons.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

The Dark Side: Security and Reliability Concerns in Machine Learning for EDA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

DyNNamic: Dynamically Reshaping, High Data-Reuse Accelerator for Compact DNNs.
IEEE Trans. Computers, March, 2023

DisP+V: A Unified Framework for Disentangling Prototype and Variation From Single Sample per Person.
IEEE Trans. Neural Networks Learn. Syst., February, 2023

Guest Editorial Machine Learning for Resilient Industrial Cyber-Physical Systems.
IEEE Trans Autom. Sci. Eng., 2023

In-Storage Acceleration of Graph-Traversal-Based Approximate Nearest Neighbor Search.
CoRR, 2023

EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research.
CoRR, 2023

DACBERT: Leveraging Dependency Agreement for Cost-Efficient Bert Pretraining.
CoRR, 2023

DistDNAS: Search Efficient Feature Interactions within 2 Hours.
CoRR, 2023

Farthest Greedy Path Sampling for Two-shot Recommender Search.
CoRR, 2023

FedBPT: Efficient Federated Black-box Prompt Tuning for Large Language Models.
CoRR, 2023

OpenOOD v1.5: Enhanced Benchmark for Out-of-Distribution Detection.
CoRR, 2023

PrivaScissors: Enhance the Privacy of Collaborative Inference through the Lens of Mutual Information.
CoRR, 2023

Towards Building the Federated GPT: Federated Instruction Tuning.
CoRR, 2023

Robust and IP-Protecting Vertical Federated Learning against Unexpected Quitting of Parties.
CoRR, 2023

SIO: Synthetic In-Distribution Data Benefits Out-of-Distribution Detection.
CoRR, 2023

Analog, In-memory Compute Architectures for Artificial Intelligence.
CoRR, 2023

NASRec: Weight Sharing Neural Architecture Search for Recommender Systems.
Proceedings of the ACM Web Conference 2023, 2023

: Joint Point Interaction-Dimension Search for 3D Point Cloud.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023

Mixture Outlier Exposure: Towards Out-of-Distribution Detection in Fine-grained Environments.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023

Interpreting Disparate Privacy-Utility Tradeoff in Adversarial Learning via Attribute Correlation.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023

ReFloat: Low-Cost Floating-Point Processing in ReRAM for Accelerating Iterative Linear Solvers.
Proceedings of the International Conference for High Performance Computing, 2023

DISQ: Dynamic Iteration Skipping for Variational Quantum Algorithms.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023

Biologically Plausible Learning on Neuromorphic Hardware Architectures.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Swirls: Sniffing Wi-Fi Using Radios with Low Sampling Rates.
Proceedings of the Twenty-fourth International Symposium on Theory, 2023

Early Identification of Timing Critical RTL Components using ML based Path Delay Prediction.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

Si-Kintsugi: Towards Recovering Golden-Like Performance of Defective Many-Core Spatial Architectures for AI.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

LISSNAS: Locality-based Iterative Search Space Shrinkage for Neural Architecture Search.
Proceedings of the Thirty-Second International Joint Conference on Artificial Intelligence, 2023

Fed-CBS: A Heterogeneity-Aware Client Sampling Mechanism for Federated Learning via Class-Imbalance Reduction.
Proceedings of the International Conference on Machine Learning, 2023

Stable and Causal Inference for Discriminative Self-supervised Deep Visual Representations.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

Communication-Efficient Vertical Federated Learning with Limited Overlapping Samples.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: Towards the Efficiency, Heterogeneity, and Robustness of Edge AI.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Accelerating Sparse Attention with a Reconfigurable Non-volatile Processing-In-Memory Architecture.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Fine-grain Inference on Out-of-Distribution Data with Hierarchical Classification.
Proceedings of the Conference on Lifelong Learning Agents, 2023

DefT: Boosting Scalability of Deformable Convolution Operations on GPUs.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-Design.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Rethink before Releasing Your Model: ML Model Extraction Attack in EDA.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

ReAugKD: Retrieval-Augmented Knowledge Distillation For Pre-trained Language Models.
Proceedings of the 61st Annual Meeting of the Association for Computational Linguistics (Volume 2: Short Papers), 2023

2022
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.
ACM Trans. Design Autom. Electr. Syst., 2022

Introduction to the Special Section on Energy-Efficient AI Chips.
ACM Trans. Design Autom. Electr. Syst., 2022

Toward Efficient and Adaptive Design of Video Detection System with Deep Neural Networks.
ACM Trans. Embed. Comput. Syst., 2022

Processing-in-Memory Technology for Machine Learning: From Basic to ASIC.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Research Progress on Memristor: From Synapses to Computing Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Preplacement Net Length and Timing Estimation by Customized Graph Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

IVQ: In-Memory Acceleration of DNN Inference Exploiting Varied Quantization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Guest Editorial: IEEE TC Special Issue On Software, Hardware and Applications for Neuromorphic Computing.
IEEE Trans. Computers, 2022

Improving Out-of-Distribution Detection by Learning From the Deployment Environment.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2022

Editorial: Machine learning for computational neural modeling and data analyses.
Frontiers Comput. Neurosci., 2022

ISLPED 2021: The 25th Anniversary!
IEEE Des. Test, 2022

PIDS: Joint Point Interaction-Dimension Search for 3D Point Cloud.
CoRR, 2022

More Generalized and Personalized Unsupervised Representation Learning In A Distributed System.
CoRR, 2022

Rethinking Normalization Methods in Federated Learning.
CoRR, 2022

FADE: Enabling Large-Scale Federated Adversarial Training on Resource-Constrained Edge Devices.
CoRR, 2022

Self-Trained Proposal Networks for the Open World.
CoRR, 2022

The Dark Side: Security Concerns in Machine Learning for EDA.
CoRR, 2022

Tolerating Noise Effects in Processing-in-Memory Systems for Neural Networks: A Hardware-Software Codesign Perspective.
Adv. Intell. Syst., 2022

The Untapped Potential of Off-the-Shelf Convolutional Neural Networks.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2022

FedSEA: A Semi-Asynchronous Federated Learning Framework for Extremely Heterogeneous Devices.
Proceedings of the 20th ACM Conference on Embedded Networked Sensor Systems, 2022

Why do We Need Large Batchsizes in Contrastive Learning? A Gradient-Bias Perspective.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

The 5th Artificial Intelligence of Things (AIoT) Workshop.
Proceedings of the KDD '22: The 28th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, Washington, DC, USA, August 14, 2022

A 1.041-Mb/mm<sup>2</sup> 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

An Audio Frequency Unfolding Framework for Ultra-Low Sampling Rate Sensors.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Security Threat to the Robustness of RRAM-based Neuromorphic Computing System.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

Cascading structured pruning: enabling high data reuse for sparse DNN accelerators.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

MOM: Microphone based 3D Orientation Measurement.
Proceedings of the 21st ACM/IEEE International Conference on Information Processing in Sensor Networks, 2022

Join-Chain Network: A Logical Reasoning View of the Multi-head Attention in Transformer.
Proceedings of the IEEE International Conference on Data Mining Workshops, 2022

GraphFL: A Federated Learning Framework for Semi-Supervised Node Classification on Graphs.
Proceedings of the IEEE International Conference on Data Mining, 2022

DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Robustify ML-Based Lithography Hotspot Detectors.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Boosting the sensing granularity of acoustic signals by exploiting hardware non-linearity.
Proceedings of the 21st ACM Workshop on Hot Topics in Networks, 2022

HERO: hessian-enhanced robust optimization for unifying and improving generalization and quantization performance.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Towards collaborative intelligence: routability estimation based on decentralized private data.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Privacy Leakage of Adversarial Training Models in Federated Learning Systems.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022

FedCor: Correlation-Based Active Client Selection Strategy for Heterogeneous Federated Learning.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

Next Generation Federated Learning for Edge Devices: An Overview.
Proceedings of the 8th IEEE International Conference on Collaboration and Internet Computing, 2022

ScaleNAS: Multi-Path One-Shot NAS for Scale-Aware High-Resolution Representation.
Proceedings of the International Conference on Automated Machine Learning, 2022

Lithography Hotspot Detection via Heterogeneous Federated Learning with Local Adaptation.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

On Building Efficient and Robust Neural Network Designs.
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022

2021
Memristive LSTM Network for Sentiment Analysis.
IEEE Trans. Syst. Man Cybern. Syst., 2021

Multilabel Image Classification via Feature/Label Co-Projection.
IEEE Trans. Syst. Man Cybern. Syst., 2021

Sliding Mode Stabilization of Memristive Neural Networks With Leakage Delays and Control Disturbance.
IEEE Trans. Neural Networks Learn. Syst., 2021

VD-GAN: A Unified Framework for Joint Prototype and Representation Learning From Contaminated Single Sample per Person.
IEEE Trans. Inf. Forensics Secur., 2021

End-to-End Detection-Segmentation System for Face Labeling.
IEEE Trans. Emerg. Top. Comput. Intell., 2021

TPrune: Efficient Transformer Pruning for Mobile Devices.
ACM Trans. Cyber Phys. Syst., 2021

Exploring Applications of STT-RAM in GPU Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Editorial Special Issue for 50th Birthday of Memristor Theory and Application of Neuromorphic Computing Based on Memristor - Part II.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Editorial Special Issue for 50th Birthday of Memristor Theory and Application of Neuromorphic Computing Based on Memristor - Part I.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Improving Write Performance on Cross-Point RRAM Arrays by Leveraging Multidimensional Non-Uniformity of Cell Effective Voltage.
IEEE Trans. Computers, 2021

Bridging a Gap in SAR-ATR: Training on Fully Synthetic and Testing on Measured Data.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2021

Training SAR-ATR Models for Reliable Operation in Open-World Environments.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2021

Combining improved genetic algorithm and matrix semi-tensor product (STP) in color image encryption.
Signal Process., 2021

Introduction to the Special Issue on Hardware and Algorithms for Efficient Machine Learning - Part 2.
ACM J. Emerg. Technol. Comput. Syst., 2021

Introduction of Special Issue on Hardware and Algorithms for Efficient Machine Learning-Part 1.
ACM J. Emerg. Technol. Comput. Syst., 2021

An efficient approach for encrypting double color images into a visually meaningful cipher image using 2D compressive sensing.
Inf. Sci., 2021

Efficient neural network using pointwise convolution kernels with linear phase constraint.
Neurocomputing, 2021

Spintronic memristors for computing.
CoRR, 2021

Harnessing Optoelectronic Noises in a Photonic Generative Adversarial Network (GAN).
CoRR, 2021

Fine-grained Out-of-Distribution Detection with Mixup Outlier Exposure.
CoRR, 2021

FedGP: Correlation-Based Active Client Selection for Heterogeneous Federated Learning.
CoRR, 2021

On Provable Backdoor Defense in Collaborative Learning.
CoRR, 2021

Explainability Metrics of Deep Convolutional Networks for Photoplethysmography Quality Assessment.
IEEE Access, 2021

FedMask: Joint Computation and Communication-Efficient Personalized Federated Learning via Heterogeneous Masking.
Proceedings of the SenSys '21: The 19th ACM Conference on Embedded Networked Sensor Systems, Coimbra, Portugal, November 15, 2021

FL-WBC: Enhancing Robustness against Model Poisoning Attacks in Federated Learning from a Client Perspective.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

Hermes: an efficient federated learning framework for heterogeneous mobile clients.
Proceedings of the ACM MobiCom '21: The 27th Annual International Conference on Mobile Computing and Networking, 2021

APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

ESCALATE: Boosting the Efficiency of Sparse CNN Accelerator with Kernel Decomposition.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

The 4th Artificial Intelligence of Things (AIoT) Workshop.
Proceedings of the KDD '21: The 27th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2021

Privacy-Preserving Representation Learning on Graphs: A Mutual Information Perspective.
Proceedings of the KDD '21: The 27th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2021

DeepObfuscator: Obfuscating Intermediate Representations with Privacy-Preserving Adversarial Learning on Smartphones.
Proceedings of the IoTDI '21: International Conference on Internet-of-Things Design and Implementation, 2021

Defending against GAN-based DeepFake Attacks via Transformation-aware Adversarial Faces.
Proceedings of the International Joint Conference on Neural Networks, 2021

LotteryFL: Empower Edge Intelligence with Personalized and Communication-Efficient Federated Learning.
Proceedings of the 6th IEEE/ACM Symposium on Edge Computing, 2021

Improving Gradient Regularization using Complex-Valued Neural Networks.
Proceedings of the 38th International Conference on Machine Learning, 2021

Disentangling Prototype and Variation for Single Sample Face Recognition.
Proceedings of the 2021 IEEE International Conference on Multimedia and Expo, 2021

BSQ: Exploring Bit-Level Sparsity for Mixed-Precision Neural Network Quantization.
Proceedings of the 9th International Conference on Learning Representations, 2021

Can Targeted Adversarial Examples Transfer When the Source and Target Models Have No Label Space Overlap?
Proceedings of the IEEE/CVF International Conference on Computer Vision Workshops, 2021

MORE<sup>2</sup>: Morphable Encryption and Encoding for Secure NVM.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Rerec: In-ReRAM Acceleration with Access-Aware Mapping for Personalized Recommendation.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

FedSwap: A Federated Learning based 5G Decentralized Dynamic Spectrum Access System.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Automatic Routability Predictor Development Using Neural Architecture Search.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Reinforcement Learning-based Black-Box Evasion Attacks to Link Prediction in Dynamic Graphs.
Proceedings of the 2021 IEEE 23rd Int Conf on High Performance Computing & Communications; 7th Int Conf on Data Science & Systems; 19th Int Conf on Smart City; 7th Int Conf on Dependability in Sensor, 2021

Hermes: Decentralized Dynamic Spectrum Access System for Massive Devices Deployment in 5G.
Proceedings of the EWSN '21: Proceedings of the 2021 International Conference on Embedded Wireless Systems and Networks, 2021

Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

RAISE: A Resistive Accelerator for Subject-Independent EEG Signal Classification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Soteria: Provable Defense Against Privacy Leakage in Federated Learning From Representation Perspective.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

AI-Powered IoT System at the Edge.
Proceedings of the Third IEEE International Conference on Cognitive Machine Intelligence, 2021

Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

NASGEM: Neural Architecture Search via Graph Embedding Method.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020
Task-Agnostic Privacy-Preserving Representation Learning via Federated Learning.
Proceedings of the Federated Learning - Privacy and Incentive, 2020

Memristor-Based Design of Sparse Compact Convolutional Neural Network.
IEEE Trans. Netw. Sci. Eng., 2020

Projective Synchroniztion of Neural Networks via Continuous/Periodic Event-Based Sampling Algorithms.
IEEE Trans. Netw. Sci. Eng., 2020

Introduction to the Special Issue on User-Centric Security and Safety for CPS.
ACM Trans. Cyber Phys. Syst., 2020

Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Thwarting Replication Attack Against Memristor-Based Neuromorphic Computing System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Low-Overhead Encoding Scheme to Extend the Lifetime of Nonvolatile Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Hiding cipher-images generated by 2-D compressive sensing with a multi-embedding strategy.
Signal Process., 2020

Color image compression and encryption scheme based on compressive sensing and double random encryption strategy.
Signal Process., 2020

Training memristor-based multilayer neuromorphic networks with SGD, momentum and adaptive learning rates.
Neural Networks, 2020

Sliding mode control of neural networks via continuous or periodic sampling event-triggering algorithm.
Neural Networks, 2020

Designing pulse-coupled neural networks with spike-synchronization-dependent plasticity rule: image segmentation and memristor circuit application.
Neural Comput. Appl., 2020

An effective image compression-encryption scheme based on compressive sensing (CS) and game of life (GOL).
Neural Comput. Appl., 2020

Exploiting plaintext-related mechanism for secure color image encryption.
Neural Comput. Appl., 2020

An efficient chaos-based image compression and encryption scheme using block compressive sensing and elementary cellular automata.
Neural Comput. Appl., 2020

Event-triggered distributed control for synchronization of multiple memristive neural networks under cyber-physical attacks.
Inf. Sci., 2020

A low-cost and high-speed hardware implementation of spiking neural network.
Neurocomputing, 2020

Quantized synchronization of memristive neural networks with time-varying delays via super-twisting algorithm.
Neurocomputing, 2020

INOR - An Intelligent noise reduction method to defend against adversarial audio examples.
Neurocomputing, 2020

Revisiting Memristor Properties.
Int. J. Bifurc. Chaos, 2020

Provable Defense against Privacy Leakage in Federated Learning from Representation Perspective.
CoRR, 2020

GraphFL: A Federated Learning Framework for Semi-Supervised Node Classification on Graphs.
CoRR, 2020

ScaleNAS: One-Shot Learning of Scale-Aware Representations for Visual Recognition.
CoRR, 2020

Fast IR Drop Estimation with Machine Learning.
CoRR, 2020

Towards Latency-aware DNN Optimization with GPU Runtime Analysis and Tail Effect Elimination.
CoRR, 2020

Low-Cost Floating-Point Processing in ReRAM for Scientific Computing.
CoRR, 2020

Evasion Attacks to Graph Neural Networks via Influence Function.
CoRR, 2020

Reinforcement Learning-based Black-Box Evasion Attacks to Link Prediction in Dynamic Graphs.
CoRR, 2020

LotteryFL: Personalized and Communication-Efficient Federated Learning with Lottery Ticket Hypothesis on Non-IID Datasets.
CoRR, 2020

NASGEM: Neural Architecture Search via Graph Embedding Method.
CoRR, 2020

TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework with Anonymized Intermediate Representations.
CoRR, 2020

Editorial for the special issue on disruptive computing technologies.
CCF Trans. High Perform. Comput., 2020

Perturbing Across the Feature Hierarchy to Improve Standard and Strict Blackbox Attack Transferability.
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020

MVStylizer: an efficient edge-assisted video photorealistic style transfer system for mobile phones.
Proceedings of the Mobihoc '20: The Twenty-first ACM International Symposium on Theory, 2020

AutoGrow: Automatic Layer Growing in Deep Convolutional Networks.
Proceedings of the KDD '20: The 26th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2020

TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework for Deep Learning with Anonymized Intermediate Representations.
Proceedings of the KDD '20: The 26th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2020

GaaS-X: Graph Analytics Accelerator Supporting Sparse Data Representation using Crossbar Architectures.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

TRP: Trained Rank Pruning for Efficient Deep Neural Networks.
Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, 2020

PENNI: Pruned Kernel Sharing for Efficient CNN Inference.
Proceedings of the 37th International Conference on Machine Learning, 2020

Transferable Perturbations of Deep Feature Distributions.
Proceedings of the 8th International Conference on Learning Representations, 2020

MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Fast IR Drop Estimation with Machine Learning : Invited Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Routing-Free Crosstalk Prediction.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

HitM: High-Throughput ReRAM-based PIM for Multi-Modal Neural Networks.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Structural Sparsification for Far-Field Speaker Recognition with Intel® Gna.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Accelerating CNN Training by Pruning Activation Gradients.
Proceedings of the Computer Vision - ECCV 2020, 2020

Neural Predictor for Neural Architecture Search.
Proceedings of the Computer Vision - ECCV 2020, 2020

ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Learning Low-rank Deep Neural Networks via Singular Vector Orthogonality Regularization and Singular Value Sparsification.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Snooping Attacks on Deep Reinforcement Learning.
Proceedings of the 19th International Conference on Autonomous Agents and Multiagent Systems, 2020

Enhancing Generalization of Wafer Defect Detection by Data Discrepancy-aware Preprocessing and Contrast-varied Augmentation.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Parallelism in Deep Learning Accelerators.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment using ReRAM.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

AutoShrink: A Topology-Aware NAS for Discovering Efficient Neural Architecture.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020

2019
Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses.
IEEE Trans. Computers, 2019

A color image cryptosystem based on dynamic DNA encryption and chaos.
Signal Process., 2019

A chaotic image encryption algorithm based on 3-D bit-plane permutation.
Neural Comput. Appl., 2019

A novel image encryption scheme based on DNA sequence operations and chaotic systems.
Neural Comput. Appl., 2019

Reshaping Future Computing Systems With Emerging Nonvolatile Memory Technologies.
IEEE Micro, 2019

Thread Batching for High-performance Energy-efficient GPU Memory Design.
ACM J. Emerg. Technol. Comput. Syst., 2019

Neuromorphic Computing Systems: From CMOS To Emerging Nonvolatile Memory.
IPSJ Trans. Syst. LSI Des. Methodol., 2019

Low-Power Computer Vision: Status, Challenges, and Opportunities.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Structural sparsification for Far-field Speaker Recognition with GNA.
CoRR, 2019

Conditional Transferring Features: Scaling GANs to Thousands of Classes with 30% Less High-quality Data for Training.
CoRR, 2019

Towards Efficient and Secure Delivery of Data for Deep Learning with Privacy-Preserving.
CoRR, 2019

DeepObfuscator: Adversarial Training Framework for Privacy-Preserving Image Classification.
CoRR, 2019

Accelerating CNN Training by Sparsifying Activation Gradients.
CoRR, 2019

SwiftNet: Using Graph Propagation as Meta-knowledge to Search Highly Representative Neural Architectures.
CoRR, 2019

Low-Power Computer Vision: Status, Challenges, Opportunities.
CoRR, 2019

Low Power Inference for On-Device Visual Recognition with a Quantization-Friendly Solution.
CoRR, 2019

ReBNN: in-situ acceleration of binarized neural networks in ReRAM using complementary resistive cell.
CCF Trans. High Perform. Comput., 2019

Resistive Memory-Based In-Memory Computing: From Device and Large-Scale Integration System Perspectives.
Adv. Intell. Syst., 2019

Markov Chain Based Efficient Defense Against Adversarial Examples in Computer Vision.
IEEE Access, 2019

Efficiently Learning a Robust Self-Driving Model with Neuron Coverage Aware Adaptive Filter Reuse.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Trained Rank Pruning for Efficient Deep Neural Networks.
Proceedings of the Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing, 2019

Hardware Fault Tolerance for Binary RRAM Crossbars.
Proceedings of the IEEE International Test Conference, 2019

Enhance the Robustness to Time Dependent Variability of ReRAM-Based Neuromorphic Computing Systems with Regularization and 2R Synapse.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

MSNet: Structural Wired Neural Architecture Search for Internet of Things.
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision Workshops, 2019

How to Obtain and Run Light and Efficient Deep Learning Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019

Learning Efficient Sparse Structures in Speech Recognition.
Proceedings of the IEEE International Conference on Acoustics, 2019

HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise Fingerprinting.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

An efficient mobile-edge collaborative system for video photorealistic style transfer.
Proceedings of the 4th ACM/IEEE Symposium on Edge Computing, 2019

An efficient edge-assisted mobile system for video photorealistic style transfer: poster abstract.
Proceedings of the 4th ACM/IEEE Symposium on Edge Computing, 2019

Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

RED: A ReRAM-based Deconvolution Accelerator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Adaptive Granularity Encoding for Energy-efficient Non-Volatile Main Memory.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

MobiEye: An Efficient Cloud-based Video Detection System for Real-time Mobile Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

ZARA: A Novel Zero-free Dataflow Accelerator for Generative Adversarial Networks in 3D ReRAM.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Feature Space Perturbations Yield More Transferable Adversarial Examples.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019

Towards Decentralized Deep Learning with Differential Privacy.
Proceedings of the Cloud Computing - CLOUD 2019, 2019

NeuralHMC: an efficient HMC-based accelerator for deep neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

AdverQuil: an efficient adversarial detection and alleviation technique for black-box neuromorphic computing systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Exploration of Automatic Mixed-Precision Search for Deep Neural Networks.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

Special Session: 2018 Low-Power Image Recognition Challenge and Beyond.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

Bamboo: Ball-Shape Data Augmentation Against Adversarial Attacks from All Directions.
Proceedings of the Workshop on Artificial Intelligence Safety 2019 co-located with the Thirty-Third AAAI Conference on Artificial Intelligence 2019 (AAAI-19), 2019

DPATCH: An Adversarial Patch Attack on Object Detectors.
Proceedings of the Workshop on Artificial Intelligence Safety 2019 co-located with the Thirty-Third AAAI Conference on Artificial Intelligence 2019 (AAAI-19), 2019

Designing Neuromorphic Computing Systems with Memristor Devices.
Proceedings of the Handbook of Memristor Networks., 2019

2018
Improving Write Performance and Extending Endurance of Object-Based NAND Flash Devices.
ACM Trans. Embed. Comput. Syst., 2018

TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

An image encryption algorithm based on chaotic system and compressive sensing.
Signal Process., 2018

Shift-Optimized Energy-Efficient Racetrack-Based Main Memory.
J. Circuits Syst. Comput., 2018

Neuromorphic computing's yesterday, today, and tomorrow - an evolutional view.
Integr., 2018

NV-TCAM: Alternative designs with NVM devices.
Integr., 2018

A Forgetting Memristive Spiking Neural Network for Pavlov Experiment.
Int. J. Bifurc. Chaos, 2018

Survey of Low-Power Electric Vehicles: A Design Automation Perspective.
IEEE Des. Test, 2018

Towards Leveraging the Information of Gradients in Optimization-based Adversarial Attack.
CoRR, 2018

Trained Rank Pruning for Efficient Deep Neural Networks.
CoRR, 2018

Adversarial Attacks for Optical Flow-Based Action Recognition Classifiers.
CoRR, 2018

LEASGD: an Efficient and Privacy-Preserving Decentralized Algorithm for Distributed Learning.
CoRR, 2018

Differentiable Fine-grained Quantization for Deep Neural Network Compression.
CoRR, 2018

2018 Low-Power Image Recognition Challenge.
CoRR, 2018

2PFPCE: Two-Phase Filter Pruning Based on Conditional Entropy.
CoRR, 2018

DPatch: Attacking Object Detectors with Adversarial Patches.
CoRR, 2018

SmoothOut: Smoothing Out Sharp Minima for Generalization in Large-Batch Deep Learning.
CoRR, 2018

Challenges of memristor based neuromorphic computing system.
Sci. China Inf. Sci., 2018

Low-Power Image Recognition Challenge.
AI Mag., 2018

Special session on reliability and vulnerability of neuromorphic computing systems.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Generalized Inverse Optimization through Online Learning.
Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018

MAT: A Multi-strength Adversarial Training Method to Mitigate Adversarial Attacks.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Design and Data Management for Magnetic Racetrack Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Learning Intrinsic Sparse Structures within Long Short-Term Memory.
Proceedings of the 6th International Conference on Learning Representations, 2018

RouteNet: routability prediction for mixed-size designs using convolutional neural network.
Proceedings of the International Conference on Computer-Aided Design, 2018

SPN dash: fast detection of adversarial attacks on mobile via sensor pattern noise fingerprinting.
Proceedings of the International Conference on Computer-Aided Design, 2018

RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

GraphR: Accelerating Graph Processing Using ReRAM.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Real-Time Cardiac Arrhythmia Classification Using Memristor Neuromorphic Computing System.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

ReRAM-based accelerator for deep learning.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

ReCom: An efficient resistive accelerator for compressed deep neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Three years of low-power image recognition challenge: Introduction to special session.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

PANEL: Open panel and discussion on tackling complexity, reproducibility and tech transfer challenges in a rapidly evolving AI/ML/systems research.
Proceedings of the 1st on Reproducible Quality-Efficient Systems Tournament on Co-designing Pareto-efficient Deep Learning, 2018

Keynote.
Proceedings of the 1st on Reproducible Quality-Efficient Systems Tournament on Co-designing Pareto-efficient Deep Learning, 2018

Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Running sparse and low-precision neural network: When algorithm meets hardware.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Spintronics based stochastic computing for efficient Bayesian inference system.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

ReGAN: A pipelined ReRAM-based accelerator for generative adversarial networks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Process variation aware data management for magnetic skyrmions racetrack memory.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Data-Pattern-Aware Error Prevention Technique to Improve System Reliability.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Exploiting Multiple Write Modes of Nonvolatile Main Memory in Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2017

Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.
IEEE Trans. Computers, 2017

Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache.
IEEE Trans. Computers, 2017

An image encryption algorithm based on the memristive hyperchaotic system, cellular automata and DNA sequence operations.
Signal Process. Image Commun., 2017

A visually secure image encryption scheme based on compressive sensing.
Signal Process., 2017

Giant Spin-Hall assisted STT-RAM and logic design.
Integr., 2017

Forgetting memristor based neuromorphic system for pattern training and recognition.
Neurocomputing, 2017

Recent Technology Advances of Emerging Memories.
IEEE Des. Test, 2017

Guest Editors' Introduction: Critical and Enabling Techniques for Emerging Memories.
IEEE Des. Test, 2017

Learning Intrinsic Sparse Structures within Long Short-term Memory.
CoRR, 2017

Generative Poisoning Attack Method Against Neural Networks.
CoRR, 2017

A Multi-strength Adversarial Training Method to Mitigate Adversarial Attacks.
CoRR, 2017

Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing.
IEEE Consumer Electron. Mag., 2017

MobiCore: An adaptive hybrid approach for power-efficient CPU management on Android devices.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A quantization-aware regularized learning method in multilevel memristor-based neuromorphic computing system.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

TernGrad: Ternary Gradients to Reduce Communication in Distributed Deep Learning.
Proceedings of the Advances in Neural Information Processing Systems 30: Annual Conference on Neural Information Processing Systems 2017, 2017

A lightweight progress maximization scheduler for non-volatile processor under unstable energy harvesting.
Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, 2017

Hardware implementation of echo state networks using memristor double crossbar arrays.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Behaviors of multi-dimensional forgetting memristor models.
Proceedings of the IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29, 2017

Faster CNNs with Direct Sparse Convolutions and Guided Pruning.
Proceedings of the 5th International Conference on Learning Representations, 2017

Coordinating Filters for Faster Deep Neural Networks.
Proceedings of the IEEE International Conference on Computer Vision, 2017

A closed-loop design to enhance weight stability of memristor based neural network chips.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

VoCaM: Visualization oriented convolutional neural network acceleration on mobile system: Invited paper.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

AdaLearner: An adaptive distributed mobile learning system for neural networks.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

An ensemble approach to activity recognition based on binary sensor readings.
Proceedings of the 19th IEEE International Conference on e-Health Networking, 2017

An FPGA Design Framework for CNN Sparsification and Acceleration.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

MoDNN: Local distributed mobile computing system for Deep Neural Network.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A Compact DNN: Approaching GoogLeNet-Level Accuracy of Classification and Domain Adaptation.
Proceedings of the 2017 IEEE Conference on Computer Vision and Pattern Recognition, 2017

Low-power neuromorphic speech recognition engine with coarse-grain sparsity.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Time, Energy, and Area Efficient Domain Wall Memory-Based SPM for Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Statistical Cache Bypassing for Non-Volatile Memory.
IEEE Trans. Computers, 2016

The bipolar and unipolar reversible behavior on the forgetting memristor model.
Neurocomputing, 2016

ApesNet: a pixel-wise efficient segmentation network for embedded devices.
IET Cyper-Phys. Syst.: Theory & Appl., 2016

Spintronic Memristor as Interface Between DNA and Solid State Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Holistic SparseCNN: Forging the Trident of Accuracy, Speed, and Size.
CoRR, 2016

Practical power consumption analysis with current smartphones.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Spin-Hall Assisted STT-RAM Design and Discussion.
Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016

MORPh: mobile OLED power friendly camera system.
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016

Objnandsim: object-based NAND flash device simulator.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

Learning Structured Sparsity in Deep Neural Networks.
Proceedings of the Advances in Neural Information Processing Systems 29: Annual Conference on Neural Information Processing Systems 2016, 2016

Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A neuromorphic ASIC design using one-selector-one-memristor crossbar.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Security of neuromorphic systems: Challenges and solutions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Heterogeneous systems with reconfigurable neuromorphic computing accelerators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Cyclical sensing integrate-and-fire circuit for memristor array based neuromorphic computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Built-in selectors self-assembled into memristors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Adaptive refreshing and read voltage control scheme for FeDRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Neural processor design enabled by memristor technology.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Design techniques of eNVM-enabled neuromorphic computing systems.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Security challenges in smart surveillance systems and the solutions based on emerging nano-devices.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Scope - quality retaining display rendering workload scaling based on user-smartphone distance.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Modeling STT-RAM fabrication cost and impacts in NVSim.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

The Applications of NVM Technology in Hardware Security.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

ApesNet: A Pixel-wise Efficient Segmentation Network.
Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016

Dictionary learning for sparse representation and classification of neural spikes.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip.
Proceedings of the 53rd Annual Design Automation Conference, 2016

TEMP: thread batch enabled memory partitioning for GPU.
Proceedings of the 53rd Annual Design Automation Conference, 2016

NVSim-VX<sup>s</sup>: an improved NVSim for variation aware STT-RAM simulation.
Proceedings of the 53rd Annual Design Automation Conference, 2016

MORPh: mobile OLED-friendly recording and playback system for low power video streaming.
Proceedings of the 53rd Annual Design Automation Conference, 2016

AOS: adaptive overwrite scheme for energy-efficient MLC STT-RAM cache.
Proceedings of the 53rd Annual Design Automation Conference, 2016

A design to reduce write amplification in object-based NAND flash devices.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

A novel PUF based on cell error rate distribution of STT-RAM.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Thermal optimization for memristor-based hybrid neuromorphic computing systems.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

SlowMo - enhancing mobile gesture-based authentication schemes via sampling rate optimization.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Footfall - GPS polling scheduler for power saving on wearable devices.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Read Performance: The Newest Barrier in Scaled STT-RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing.
IEEE Trans. Multi Scale Comput. Syst., 2015

RRAM-Based Analog Approximate Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache.
IEEE Trans. Computers, 2015

Reconfigurable Neuromorphic Computing System with Memristor-Based Synapse Design.
Neural Process. Lett., 2015

Circuit design and exponential stabilization of memristive neural networks.
Neural Networks, 2015

Hardware acceleration for neuromorphic computing: An evolving view.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Fork path: improving efficiency of ORAM by removing redundant memory accesses.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Memristor Crossbar Array for Image Storing.
Proceedings of the Advances in Neural Networks - ISNN 2015, 2015

A new self-reference sensing scheme for TLC MRAM.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

The applications of memristor devices in next-generation cortical processor designs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

EDA Challenges for Memristor-Crossbar based Neuromorphic Computing.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Giant spin hall effect (GSHE) logic design for low power application.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Spiking neural network with RRAM: can we use it for real-world application?
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

An EDA framework for large scale hybrid neuromorphic computing systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015

VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A spiking neuromorphic design with resistive crossbar.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Cloning your mind: security challenges in cognitive system designs and their solutions.
Proceedings of the 52nd Annual Design Automation Conference, 2015

RENO: a high-efficient reconfigurable neuromorphic computing accelerator design.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Vortex: variation-aware training for memristor X-bar.
Proceedings of the 52nd Annual Design Automation Conference, 2015

FlexLevel: a novel NAND flash storage system design for LDPC latency reduction.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Area and performance co-optimization for domain wall memory in application-specific embedded systems.
Proceedings of the 52nd Annual Design Automation Conference, 2015

DaTuM: dynamic tone mapping technique for OLED display power saving based on video classification.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Spiking-based matrix computation by leveraging memristor crossbar array.
Proceedings of the 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2015

Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

An efficient STT-RAM-based register file in GPU architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Recent progresses of STT memory design and applications.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
User Classification and Authentication for Mobile Device Based on Gesture Recognition.
Proceedings of the Network Science and Cybersecurity, 2014

Memristor Crossbar-Based Neuromorphic Computing System: A Case Study.
IEEE Trans. Neural Networks Learn. Syst., 2014

PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Memristor crossbar-based unsupervised image learning.
Neural Comput. Appl., 2014

NV-TCAM: Alternative interests and practices in NVM designs.
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Memristive Radial Basis Function Neural Network for Parameters Adjustment of PID Controller.
Proceedings of the Advances in Neural Networks - ISNN 2014, 2014

SBAC: a statistics based cache bypassing method for asymmetric-access caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper).
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Bio-inspired computing with resistive memories - models, architectures and applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An adjustable memristor model and its application in small-world neural networks.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

STDP learning rule based on memristor with STDP property.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

Reduction of data prevention cost and improvement of reliability in MLC NAND flash storage system.
Proceedings of the International Conference on Computing, Networking and Communications, 2014

Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A heterogeneous computing system with memristor-based neuromorphic accelerators.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

Mobile GPU Power Consumption Reduction via Dynamic Resolution and Frame Rate Scaling.
Proceedings of the 6th Workshop on Power-Aware Computing and Systems, 2014

FingerShadow: An OLED Power Optimization Based on Smartphone Touch Interactions.
Proceedings of the 6th Workshop on Power-Aware Computing and Systems, 2014

ICE: Inline calibration for memristor crossbar-based computing engine.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy efficient neural networks for big data analytics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

eButton: A Wearable Computer for Health Monitoring and Personal Assistance.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Demystifying Energy Usage in Smartphones.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

3M-PCM: Exploiting multiple write modes MLC phase change main memory in embedded systems.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Prefetching techniques for STT-RAM based last-level cache in CMP systems.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Training itself: Mixed-signal training acceleration for memristor-based neural network.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

DPA: A data pattern aware error prevention technique for NAND flash lifetime extension.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.
ACM Trans. Design Autom. Electr. Syst., 2013

Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh.
ACM Trans. Design Autom. Electr. Syst., 2013

C1C: A configurable, compiler-guided STT-RAM L1 cache.
ACM Trans. Archit. Code Optim., 2013

Online OLED dynamic voltage scaling for video streaming applications on mobile devices.
SIGBED Rev., 2013

Reliability-aware energy minimization for real-time embedded systems with window-constraints.
SIGBED Rev., 2013

Global exponential synchronization of memristor-based recurrent neural networks with time-varying delays.
Neural Networks, 2013

Passivity analysis of memristor-based recurrent neural networks with time-varying delays.
J. Frankl. Inst., 2013

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.
ACM J. Emerg. Technol. Comput. Syst., 2013

How is energy consumed in smartphone display applications?
Proceedings of the 14th Workshop on Mobile Computing Systems and Applications, 2013

Memristor-based approximated computation.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

MLC STT-RAM design considering probabilistic and asymmetric MTJ switching.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Considering fabrication in sustainable computing.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Coordinating prefetching and STT-RAM based last-level cache management for multicore systems.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Cache coherence enabled adaptive refresh for volatile STT-RAM.
Proceedings of the Design, Automation and Test in Europe, 2013

Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer.
Proceedings of the Design, Automation and Test in Europe, 2013

DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Online OLED dynamic voltage scaling for video streaming applications on mobile devices.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

BSB training scheme implementation on memristor-based circuit.
Proceedings of the 2013 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2013

Loadsa: A yield-driven top-down design method for STT-RAM array.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Mobile user classification and authorization based on gesture usage recognition.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Low-Power Design of Emerging Memory Technologies.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme.
IEEE J. Solid State Circuits, 2012

Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder.
ACM J. Emerg. Technol. Comput. Syst., 2012

Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration.
IEEE Embed. Syst. Lett., 2012

Neuromorphic computing: A SoC scaling path for the next decades.
Proceedings of the IEEE 25th International SOC Conference, 2012

Utilizing PCM for Energy Optimization in Embedded Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Improving energy efficiency of write-asymmetric memories by log style write.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

A software approach for combating asymmetries of non-volatile memories.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Memristor crossbar based hardware realization of BSB recall function.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

The Circuit Realization of a Neuromorphic Computing System with Memristor-Based Synapse Design.
Proceedings of the Neural Information Processing - 19th International Conference, 2012

Multi-level cell STT-RAM: Is it realistic or just a dream?
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

A thermal and process variation aware MTJ switching model and its applications in soft error analysis.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Mobile devices user - The subscriber and also the publisher of real-time OLED display power management plan.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Architecting a common-source-line array for bipolar non-volatile memory devices.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Asymmetry of MTJ switching and its implication to STT-RAM designs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Spintronic memristor based temperature sensor design with CMOS current reference.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Statistical memristor modeling and case study in neuromorphic computing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Probabilistic design in spintronic memory and logic circuit.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Fine-grained dynamic voltage scaling on OLED display.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM).
IEEE Trans. Very Large Scale Integr. Syst., 2011

Spintronic Memristor: Compact Model and Statistical Analysis.
J. Low Power Electron., 2011

Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.
IET Comput. Digit. Tech., 2011

Processor caches with multi-level spin-transfer torque ram cells.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers.
Proceedings of the Design, Automation and Test in Europe, 2011

Emerging non-volatile memories: opportunities and challenges.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Geometry variations analysis of TiO2 thin-film and spintronic memristors.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Emerging sensing techniques for emerging memories.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Scalability of PCMO-based resistive switch device in DSM technologies.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Low-power dual-element memristor based memory design.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Spintronic memristor devices and application.
Proceedings of the Design, Automation and Test in Europe, 2010

A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM).
Proceedings of the Design, Automation and Test in Europe, 2010

Impact of process variations on emerging memristor.
Proceedings of the 47th Design Automation Conference, 2010

2009
Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Tolerating process variations in large, set-associative caches: The buddy cache.
ACM Trans. Archit. Code Optim., 2009

Compact modeling and corner analysis of spintronic memristor.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies.
Proceedings of the 27th International Conference on Computer Design, 2009

A novel architecture of the 3D stacked MRAM L2 cache for CMPs.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

An overview of non-volatile memory technology and the implication for tools and architectures.
Proceedings of the Design, Automation and Test in Europe, 2009

Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.
Proceedings of the 46th Design Automation Conference, 2009

2008
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM).
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.
Proceedings of the 45th Design Automation Conference, 2008

2007
Statistical Timing Analysis Considering Spatial Correlations.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

VOSCH: Voltage scaled cache hierarchies.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Cascaded carry-select adder (C<sup>2</sup>SA): a new structure for low-power CSA design.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Statistical based link insertion for robust clock network design.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004
DCG: deterministic clock-gating for low-power microprocessor design.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Deterministic Clock Gating for Microprocessor Power Reduction.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods.
Proceedings of the 2002 Design, 2002


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