Yiqiang Ding

According to our database, Yiqiang Ding authored at least 20 papers between 1999 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Exploiting Static Non-Uniform Cache Architectures for Hard Real-Time Computing.

Yiqiang Ding, Wei Zhang

J. Comput. Sci. Eng., 2015

2014

Exploiting Standard Deviation of CPI to Evaluate Architectural Time-Predictability.

Wei Zhang, Yiqiang Ding

J. Comput. Sci. Eng., 2014

Comparing Separate and Statically-Partitioned Caches for Time-Predictable Multicore Processors.

Lan Wu, Yiqiang Ding, Wei Zhang

J. Comput. Sci. Eng., 2014

WCET analysis of static NUCA caches.

Yiqiang Ding, Wei Zhang

Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

Characterizing Energy Consumption of Real-Time and Media Benchmarks on Hybrid SPM-Caches.

Lan Wu, Yiqiang Ding, Wei Zhang

Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Bounding the Worst-Case Execution Time of Static NUCA Caches.

Yiqiang Ding, Wei Zhang

Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Hop-Based Priority Scheduling to Improve Worst-Case Inter-core Communication Latency.

Yiqiang Ding, Wei Zhang

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2013

Bounding Worst-Case DRAM Performance on Multicore Processors.

Yiqiang Ding, Lan Wu, Wei Zhang

J. Comput. Sci. Eng., 2013

Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared Caches.

Yiqiang Ding, Wei Zhang

J. Comput. Sci. Eng., 2013

Multicore Real-Time Scheduling to Reduce Inter-Thread Cache Interferences.

Yiqiang Ding, Wei Zhang

J. Comput. Sci. Eng., 2013

On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors.

Yiqiang Ding, Wei Zhang

Proceedings of the International Symposium on Quality Electronic Design, 2013

Hybrid SPM-cache architectures to achieve high time predictability and performance.

Wei Zhang, Yiqiang Ding

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Standard deviation of CPI: A new metric to evaluate architectural time predictability.

Wei Zhang, Yiqiang Ding

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012

Architectural time-predictability factor (ATF): a metric to evaluate time predictability of processors.

Yiqiang Ding, Wei Zhang

SIGBED Rev., 2012

Multicore-Aware Code Co-Positioning to Reduce WCET on Dual-Core Processors with Shared Instruction Caches.

Yiqiang Ding, Wei Zhang

J. Comput. Sci. Eng., 2012

2011

Multicore-Aware Code Positioning to Improve Worst-Case Performance.

Yiqiang Ding, Wei Zhang

Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2011

2010

Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time.

Yiqiang Ding, Wei Zhang

IEEE Trans. Computers, 2010

Improving the static real-time scheduling on multicore processors by reducing worst-case inter-thread cache interferences.

Yiqiang Ding, Wei Zhang

Proceedings of the 48th Annual Southeast Regional Conference, 2010

2009

Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications.

Yiqiang Ding, Jun Yan, Wei Zhang

J. Comput. Sci. Eng., 2009

1999

An improvement of GNY logic for the reflection attacks.

Yiqiang Ding

J. Comput. Sci. Technol., 1999