Yiping Dong
Orcid: 0000-0002-4866-9542
According to our database1,
Yiping Dong
authored at least 16 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Enhancing Visual Question Answering through Ranking-Based Hybrid Training and Multimodal Fusion.
CoRR, 2024
The Design of Autonomous UAV Prototypes for Inspecting Tunnel Construction Environment.
CoRR, 2024
2022
Wirel. Pers. Commun., 2022
DPMPC-Planner: A real-time UAV trajectory planning framework for complex static environments with dynamic obstacles.
Proceedings of the 2022 International Conference on Robotics and Automation, 2022
2020
Multi-Shape Task Placement Algorithm Based on Low Fragmentation Resource Management on 2D Heterogeneous Dynamic Partial Reconfigurable Devices.
IEEE Access, 2020
A Fast Online Task Placement Algorithm for Three-Dimensional Dynamic Partial Reconfigurable Devices.
IEEE Access, 2020
IEEE Access, 2020
An Interval-based Mapping Algorithm for Multi-shape Tasks on Dynamic Partial Reconfigurable FPGAs.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020
2019
J. Comput. Biol., 2019
2018
Integrated Bioinformatics Analysis for Identificating the Therapeutic Targets of Aspirin in Small Cell Lung Cancer.
J. Biomed. Informatics, 2018
2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture.
IEICE Trans. Inf. Syst., 2012
2011
Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
2010
High performance implementation of Neural Networks by networks on chip with 5-port 2-virtual channels.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A hybrid architecture for efficient FPGA-based implementation of multilayer neural network.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010