Yipin Wu

According to our database, Yipin Wu authored at least 3 papers between 2007 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Stack effect and logic restructuring on high Fan-in FinFETs logic gates.

Senthilkumar Jayapal, Janani Sainath Sigundey, Yipin Wu, EricT Tsai

Proceedings of the International Symposium on Integrated Circuits, 2016

2014

A novel power noise simulation methodology for chip design using Wafer Level Chip Scale Packaging.

Yipin Wu, Zhigang Hao, Jingchun Han, Joy Tsai

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

2007

Quasi-Static Energy Recovery Logic with Single Power-Clock Supply.

Shun Li, Feng Zhou, Chunhong Chen, Hua Chen, Yipin Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007