Yiorgos Makris
Orcid: 0000-0002-4322-0068
According to our database1,
Yiorgos Makris
authored at least 221 papers
between 1998 and 2024.
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Bibliography
2024
Bit-by-Bit: Investigating the Vulnerabilities of Binary Neural Networks to Adversarial Bit Flipping.
Trans. Mach. Learn. Res., 2024
IEEE Des. Test, 2024
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
NSPG: Natural language Processing-based Security Property Generator for Hardware Security Assurance.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
Machine Learning-Based Adaptive Outlier Detection for Underkill Reduction in Analog/RF IC Testing.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the 32nd USENIX Security Symposium, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Proceedings of the 2022 IEEE International Conference on Image Processing, 2022
Physically and Algorithmically Secure Logic Locking with Hybrid CMOS/Nanomagnet Logic Circuits.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Bias Busters: Robustifying DL-Based Lithographic Hotspot Detectors Against Backdooring Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Proof-Carrying Hardware-Based Information Flow Tracking in Analog/Mixed-Signal Designs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Improved Static Hand Gesture Classification on Deep Convolutional Neural Networks Using Novel Sterile Training Technique.
IEEE Access, 2021
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Amplitude-Modulating Analog/RF Hardware Trojans in Wireless Networks: Risks and Remedies.
IEEE Trans. Inf. Forensics Secur., 2020
A Hardware-Based Architecture-Neutral Framework for Real-Time IoT Workload Forensics.
IEEE Trans. Computers, 2020
ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Range-Controlled Floating-Gate Transistors: A Unified Solution for Unlocking and Calibrating Analog ICs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020
2019
Demonstrating and Mitigating the Risk of an FEC-Based Hardware Trojan in Wireless Networks.
IEEE Trans. Inf. Forensics Secur., 2019
Integr., 2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Post-Production Calibration of Analog/RF ICs: Recent Developments and A Fully Integrated Solution.
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019
VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration.
Proceedings of the IEEE International Test Conference, 2019
Subtle Anomaly Detection of Microscopic Probes using Deep learning based Image Completion.
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage.
Proceedings of the International Conference on Field-Programmable Technology, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Enhanced hotspot detection through synthetic pattern generation and design of experiments.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Hardware Dithering: A Run-Time Method for Trojan Neutralization in Wireless Cryptographic ICs.
Proceedings of the IEEE International Test Conference, 2018
On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs.
Proceedings of the IEEE International Test Conference, 2018
Hardware-assisted rootkit detection via on-line statistical fingerprinting of process execution.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Silicon Demonstration of Hardware Trojan Design and Detection in Wireless Cryptographic ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part I: Framework Fundamentals.
IEEE Trans. Inf. Forensics Secur., 2017
Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part II: Framework Automation.
IEEE Trans. Inf. Forensics Secur., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Des. Test, 2017
Knob non-idealities in learning-based post-production tuning of analog/RF ICs: Impact & remedies.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
ACE: Adaptive channel estimation for detecting analog/RF trojans in WLAN transceivers.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
INFECT: INconspicuous FEC-based Trojan: A hardware attack on an 802.11a/g wireless network.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Information flow tracking in analog/mixed-signal designs through proof-carrying hardware IP.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
-197dBc/Hz FOM 4.3-GHz VCO Using an addressable array of minimum-sized nmos cross-coupled transistor pairs in 65-nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Hardware-based attacks to compromise the cryptographic security of an election system.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
2015
Multiple-Bit Upset Protection in Microprocessor Memory Arrays Using Vulnerability-Based Parity Optimization and Interleaving.
IEEE Trans. Very Large Scale Integr. Syst., 2015
An Experimentation Platform for On-Chip Integration of Analog Neural Networks: A Pathway to Trusted and Robust Analog/RF ICs.
IEEE Trans. Neural Networks Learn. Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Computers, 2015
Low-Cost Analog/RF IC Testing Through Combined Intra- and Inter-Die Correlation Models.
IEEE Des. Test, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 2015 IEEE International Test Conference, 2015
Proceedings of the 2015 IEEE International Test Conference, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Toward automatic proof generation for information flow policies in third-party hardware IP.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
2014
Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain.
Proc. IEEE, 2014
On-chip intelligence: A pathway to self-testable, tunable, and trusted analog/RF ICs.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the 2014 International Test Conference, 2014
Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation.
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Hardware Trojan Detection through Golden Chip-Free Statistical Side-Channel Fingerprinting.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
IEEE Trans. Computers, 2013
J. Electron. Test., 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
Counterfeit electronics: A rising threat in the semiconductor manufacturing industry.
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Hardware Trojans in wireless cryptographic ICs: silicon demonstration & detection method evaluation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Cycle-accurate information assurance by proof-carrying based signal sensitivity tracing.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition.
IEEE Trans. Inf. Forensics Secur., 2012
Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors.
IEEE Trans. Computers, 2012
IEEE Des. Test Comput., 2012
Towards a fully stand-alone analog/RF BIST: A cost-effective implementation of a neural classifier.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proof carrying-based information flow tracking for data secrecy protection and hardware trust.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Vulnerability-based Interleaving for Multi-Bit Upset (MBU) protection in modern microprocessors.
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller.
IEEE Trans. Computers, 2011
Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor.
IEEE Trans. Computers, 2011
Guest Editors' Introduction: Special Section on Chips and Architectures for Emerging Technologies and Applications.
IEEE Trans. Computers, 2011
IEEE Des. Test Comput., 2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the HOST 2011, 2011
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Workload-driven selective hardening of control state elements in modern microprocessors.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits.
IEEE Trans. Computers, 2009
On Boosting the Accuracy of Non-RF to RF Correlation-Based Specification Test Compaction.
J. Electron. Test., 2009
Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009
Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Reliab., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors.
Proceedings of the 2008 IEEE International Test Conference, 2008
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008
Confidence Estimation in Non-RF to RF Correlation-Based Specification Test Compaction.
Proceedings of the 13th European Test Symposium, 2008
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008
2007
IEEE Trans. Computers, 2007
On the identification of modular test requirements for low cost hierarchical test path construction.
Integr., 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Microelectron. J., 2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test.
IEEE Trans. Reliab., 2004
J. Electron. Test., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 2004 Design, 2004
2003
IEEE Trans. Instrum. Meas., 2003
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees.
Proceedings of the 2003 Design, 2003
2002
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface.
J. Electron. Test., 2002
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line Test.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 5th European Test Workshop, 2000
Modular test generation and concurrent transparency-based test translation using gate-level ATPG.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 1999 Design, 1999
TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generation.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
J. Electron. Test., 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998