Yinghua Min

According to our database1, Yinghua Min authored at least 55 papers between 1982 and 2011.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 1997, "For technical leadership in electronic testing and fault-tolerant computing.".

Timeline

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Bibliography

2011
Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
Automatic string test data generation for detecting domain errors.
Softw. Test. Verification Reliab., 2010

2009
Impact of Hazards on Pattern Selection for Small Delay Defects.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

2008
Accurate Online Traffic Classification with Multi-Phases Identification Methodology.
Proceedings of the 5th IEEE Consumer Communications and Networking Conference, 2008

2007
Survey on Traffic of Metro Area Network with Measurement On-Line.
Proceedings of the Managing Traffic Performance in Converged Networks, 2007

A Scalable Bloom Filter for Membership Queries.
Proceedings of the Global Communications Conference, 2007

Test Education in the Global Economy.
Proceedings of the 16th Asian Test Symposium, 2007

2005
Optimal, and reliable communication in hypercubes using extended safety vectors.
IEEE Trans. Reliab., 2005

An Improved Scheme of Index-Based Checkpointing.
Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

2004
Design & Test Education in Asia.
IEEE Des. Test Comput., 2004

2003
A Novel RT-Level Behavioral Description Based ATPG Method.
J. Comput. Sci. Technol., 2003

IDDT: Fundamentals and Test Generation.
J. Comput. Sci. Technol., 2003

Fault-Tolerant Systems with Concurrent Error-Locating Capability.
J. Comput. Sci. Technol., 2003

A New Software Testing Approach Based on Domain Analysis of Specifications and Programs.
Proceedings of the 14th International Symposium on Software Reliability Engineering (ISSRE 2003), 2003

Domain Testing Based on Character String Predicate.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

At-Speed Current Testing.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Why RTL ATPG?
J. Comput. Sci. Technol., 2002

The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications.
Sci. China Ser. F Inf. Sci., 2002

Clustering of behavioral phases in FSMs and its applications to VLSI test.
Sci. China Ser. F Inf. Sci., 2002

Test Power Optimization Techniques for CMOS Circuits.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Node Grouping in System-Level Fault Diagnosis.
J. Comput. Sci. Technol., 2001

Reducing Power Dissipation during At-Speed Test Application.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

An Approach to RTL Fault Extraction and Test Generation.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

An RT-Level ATPG Based on Clustering of Circuit States.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Reduction of Number of Paths to be Tested in Delay Testing.
J. Electron. Test., 2000

Optimal Fault-Tolerant Routing in Hypercubes Using Extended Safety Vectors.
Proceedings of the Seventh International Conference on Parallel and Distributed Systems, 2000

A waveform simulator based on Boolean process.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

An efficient BIST design using LFSR-ROM architecture.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
An analytical delay model.
J. Comput. Sci. Technol., 1999

A Novel NMR Structure with Concurrent Error Location Capabilities.
Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing (PRDC 1999), 1999

1998
On concurrent multiple error diagnosability in linear analog circuits using continuous checksum.
Int. J. Circuit Theory Appl., 1998

IDDT Testing versus IDDQ Testing.
J. Electron. Test., 1998

A New Low-Cost Method for Identifying Untestable Path Delay Faults.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Delay Testing with Double Observations.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Path sensitization.
J. Comput. Sci. Technol., 1997

Short-time scaling of variable ordering of OBDDs.
J. Comput. Sci. Technol., 1997

Efficient Identification of Non-Robustly Untestable Path Delay Faults.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Timed Binary Decision Diagrams.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Design of delay-verifiable combinational logic by adding extra inputs.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

IDDT Testing.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Memory Efficient ATPG for Path Delay Faults.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
A kind of Multistage Interconnection Networks with multiple paths.
J. Comput. Sci. Technol., 1996

Hardware reduction in continuous checksum-based analog checkers: Algorithm and its analysis.
J. Electron. Test., 1996

An Analytical Delay Model Based on Boolean Process.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Waveform Polynomial Manipulation Using Bdds.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
A fault-tolerant and heuristic routing algorithm for faulty hypercubes.
J. Comput. Sci. Technol., 1995

Feasibility and Effectiveness of the Algorithm for Overhead Reduction in Analog Checkers.
Proceedings of the Digest of Papers: FTCS-25, 1995

Boolean process-an analytical approach to circuit representation (II).
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Panel: New Research Problems in the Emerging Test Technology.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994
Behavioral Design and Prototyping of a Fail-Safe System.
Proceedings of the Seventh International Conference on VLSI Design, 1994

1993
Evaluation of test generation algorithms.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

1991
Analysis of Detection Capability of Parallel Signature Analyzers.
IEEE Trans. Computers, 1991

1988
Strongly fault secure PLAs and totally self-checking checkers.
IEEE Trans. Computers, 1988

1986
Pseudo-Exhaustive Testing Strategy for Large Combinational Circuits.
Comput. Syst. Sci. Eng., 1986

1982
Testing functional faults in VLSI.
Proceedings of the 19th Design Automation Conference, 1982


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