Yingchun Lu

Orcid: 0000-0002-2621-0933

According to our database¹, Yingchun Lu authored at least 41 papers between 2017 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2024

NEST: A Quadruple-Node Upset Recovery Latch Design and Algorithm-Based Recovery Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Aerosp. Electron. Syst., August, 2024

Lightweight Hybrid Entropy Source True Random Number Generator Based on Jitter and Metastability.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision.

[BibT_eX]

[DOI]

J. Electron. Test., June, 2024

A Symmetric Bridge-Based Pre-Bond TSV Faults Detection Method.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2024

A Scan-Chain-Based Built-in Self-Test for ILV in Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2024

High-throughput true random number generator based on a dual-input oscillation circuit.

[BibT_eX]

[DOI]

Microelectron. J., 2024

A lightweight reversible multi-mode physical unclonable function.

[BibT_eX]

[DOI]

Microelectron. J., 2024

High throughput dynamic dual entropy source true random number generator based on FPGA.

[BibT_eX]

[DOI]

Microelectron. J., 2024

Multi-transition delay test for improving the coverage of cell internal defects.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2024

A machine learning resistant PUF circuit adjustment method based on strict avalanche criterion.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2024

PFO PUF: A Lightweight Parallel Feed Obfuscation PUF Resistant to Machine Learning Attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2024

2023

High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., December, 2023

Low-overhead TRNG based on MUX for cryptographic protection using multiphase sampling.

[BibT_eX]

[DOI]

Liang Yao

Huaguo Liang

Yingchun Lu

J. Supercomput., October, 2023

Electrical activity and synchronization of memristor synapse-coupled HR network based on energy method.

[BibT_eX]

[DOI]

Yingchun Lu

Hongmin Li

Chun-Lai Li

Neurocomputing, August, 2023

Design of approximate Booth multipliers based on error compensation.

[BibT_eX]

[DOI]

Integr., May, 2023

A dynamically reconfigurable entropy source circuit for high-throughput true random number generator.

[BibT_eX]

[DOI]

Microelectron. J., March, 2023

Improvement of cell internal weak defects detection under process variation by optimizing test path and test pattern.

[BibT_eX]

[DOI]

Microelectron. J., 2023

Fault-avoidance C-element based low overhead and TNU-resilient latch.

[BibT_eX]

[DOI]

Microelectron. J., 2023

2022

A router architecture with dual input and dual output channels for Networks-on-Chip.

[BibT_eX]

[DOI]

Microprocess. Microsystems, April, 2022

DCBuf: a high-performance wireless network-on-chip architecture with distributed wireless interconnects and centralized buffer sharing.

[BibT_eX]

[DOI]

Chenglong Sun

Yiming Ouyang

Yingchun Lu

Wirel. Networks, 2022

Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

M-RO PUF: A portable pure digital RO PUF based on MUX unit.

[BibT_eX]

[DOI]

Microelectron. J., 2022

A reconfigurable PUF structure with dual working modes based on entropy separation model.

[BibT_eX]

[DOI]

Microelectron. J., 2022

Design of fully adaptive routing and hybrid VC allocation in wireless NOC.

[BibT_eX]

[DOI]

Microelectron. J., 2022

Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2022

A reconfigurable test method based on LFSR for 3D stacking integrated circuits.

[BibT_eX]

[DOI]

Integr., 2022

A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design.

[BibT_eX]

[DOI]

J. Electron. Test., 2022

A Lightweight M_TRNG Design based on MUX Cell Entropy using Multiphase Sampling.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

2021

Pure Digital Scalable Mixed Entropy Separation Structure for Physical Unclonable Function and True Random Number Generator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A high reliability physically unclonable function based on multiple tunable ring oscillator.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Design of MNU-Resilient latches based on input-split C-elements.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Design of node separated triple-node-upset self-recoverable latch.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2021

Approximate multipliers based on a novel unbiased approximate 4-2 compressor.

[BibT_eX]

[DOI]

Integr., 2021

Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems.

[BibT_eX]

[DOI]

J. Electron. Test., 2021

2020

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm.

[BibT_eX]

[DOI]

IEEE Access, 2020

Jitter-Quantizing-Based TRNG Robust Against PVT Variations.

[BibT_eX]

[DOI]

IEEE Access, 2020

2018

An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

A transient pulse dually filterable and online self-recoverable latch.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

A single event transient detector in SRAM-based FPGAs.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Yingchun Lu

Timeline

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On csauthors.net:

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