Ying Zhang

Affiliations:
  • Intel Corporation, Santa Clara, CA, USA
  • Louisiana State University, School of Electrical Engineering and Computer Science, Baton Rouge, LA, USA (PhD 2013)


According to our database1, Ying Zhang authored at least 21 papers between 2010 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
LIBRA: Clearing the Cloud Through Dynamic Memory Bandwidth Management.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2017
Using Switchable Pins to Increase Off-Chip Bandwidth in Chip-Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 2017

QoS Management on Heterogeneous Architecture for Multiprogrammed, Parallel, and Domain-Specific Applications.
IEEE Syst. J., 2017

2016
Design space exploration for device and architectural heterogeneity in chip-multiprocessors.
Microprocess. Microsystems, 2016

2015
Powering Up Dark Silicon: Mitigating the Limitation of Power Delivery via Dynamic Pin Switching.
IEEE Trans. Emerg. Top. Comput., 2015

Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors.
Microprocess. Microsystems, 2015

NBTI alleviation on FinFET-made GPUs by utilizing device heterogeneity.
Integr., 2015

2014
Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules.
IEEE Trans. Computers, 2014

Design configuration selection for hard-error reliable processors via statistical rules.
Microprocess. Microsystems, 2014

Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Increasing off-chip bandwidth in multi-core processors with switchable pins.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

QoS management on heterogeneous architecture for parallel applications.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
Lighting the dark silicon by exploiting heterogeneity on future processors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Optimal microarchitectural design configuration selection for processor hard-error reliability.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011
Performance and Power Analysis of ATI GPU: A Statistical Approach.
Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

Universal rules guided design parameter selection for soft error resilient processors.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

Architecture comparisons between Nvidia and ATI GPUs: Computation parallelism and data communications.
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

Tree structured analysis on GPU power study.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Statistical GPU power analysis using tree-based methods.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

2010
Expediating IP lookups with reduced power via TBM and SST supernode caching.
Comput. Commun., 2010


  Loading...