Ying Yi
Orcid: 0000-0003-1692-6118
According to our database1,
Ying Yi
authored at least 39 papers
between 2002 and 2024.
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On csauthors.net:
Bibliography
2024
Asia Pac. J. Oper. Res., June, 2024
A Geodetic-Data-Calibrated Ice Flow Model to Simulate Historical and Future Response of Glaciers in Southeastern Tibetan Plateau.
Remote. Sens., February, 2024
Proceedings of the 16th International Conference on Education Technology and Computers, 2024
2023
Sensors, January, 2023
2020
Wireless Hyperthermia Stent System for Restenosis Treatment and Testing With Swine Model.
IEEE Trans. Biomed. Eng., 2020
Surging Dynamics of Glaciers in the Hunza Valley under an Equilibrium Mass State since 1990.
Remote. Sens., 2020
2019
Sensors, 2019
2018
Nucleic Acids Res., 2018
2017
Nucleic Acids Res., 2017
2016
A general method for cupping artifact correction of cone-beam breast computed tomography images.
Int. J. Comput. Assist. Radiol. Surg., 2016
2015
Nucleic Acids Res., 2015
Design and optimization of a 3-coil resonance-based wireless power transfer system for biomedical implants.
Int. J. Circuit Theory Appl., 2015
Electromagnetically powered electrolytic pump and thermo-responsive valve for drug delivery.
Proceedings of the 10th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2015
2014
Proceedings of the BIODEVICES 2014, 2014
2013
Surface tension-induced high aspect-ratio PDMS micropillars with concave and convex lens tips.
Proceedings of the 8th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2013
Proceedings of the 8th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2013
2010
A high-efficiency reconfigurable 2-D Discrete Wavelet Transform engine for JPEG2000 implementation on next generation digital cameras.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Dual-core reconfigurable demosaicing engine for next generation of portable camera systems.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
2009
Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Heterogeneous multi-core architectures with dynamically reconfigurable processors for WiMAX transmitter.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Heterogeneous multi-core architectures with dynamically reconfigurable processors for wireless communication.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Efficient Implementation of WiMAX Physical Layer on Multi-core Architectures with Dynamically Reconfigurable Processors.
Scalable Comput. Pract. Exp., 2008
Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008
Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
Efficient Implementation of Wireless Applications on Multi-core Platforms Based on Dynamically Reconfigurable Processors.
Proceedings of the Second International Conference on Complex, 2008
2007
Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture.
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the Integration and Innovation Orient to E-Society, 2007
H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the FPL 2007, 2007
H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based Architecture.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
J. VLSI Signal Process., 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2002
FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002