Ying Wu
Orcid: 0000-0003-2459-2605Affiliations:
- Delft University of Technology, Department of Microelectronics, The Netherlands
- Lund University, Department of Electrical and Information Technology, Sweden (former)
According to our database1,
Ying Wu
authored at least 8 papers
between 2011 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
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on orcid.org
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Bibliography
2020
A Time-Domain 147fs<sub>rms 2.5</sub>-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
2017
A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase Noise.
IEEE J. Solid State Circuits, 2017
2016
A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A 0.5ps 1.4mW 50MS/s Nyquist bandwidth time amplifier based two-step flash-ΔΣ time-to-digital converter.
Proceedings of the Second International Conference on Event-based Control, 2016
2012
A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011