Ying Fei Teh

According to our database, Ying Fei Teh authored at least 4 papers between 2011 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels.

Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme.

Ying Fei Teh, Zhiliang Qian, Chi-Ying Tsui

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources.

Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Designs for improving the performance of an electro-thermal in-plane actuator.

Alex Man Ho Kwan, Sichao Song, Xing Lu, Lei Lu, Ying-Khai Teh, Ying Fei Teh, Eddie Wing Cheung Chong, Yan Gao, William Hau, Fan Zeng, Man Wong, Chunmei Huang, Akira Taniyama, Yoshihide Makino, So Nishino, Toshiyuki Tsuchiya, Osamu Tabata

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011