Ying-Cherng Lan

According to our database1, Ying-Cherng Lan authored at least 10 papers between 2008 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2016
A BiNoC architecture - aware task allocation and communication scheduling scheme.
Microprocess. Microsystems, 2016

2015
A novel flow fluidity meter for BiNoC bandwidth resource allocation.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

2012
Networks on Chips: Structure and Design Methodologies.
J. Electr. Comput. Eng., 2012

2011
A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010
DyML: Dynamic Multi-Level flow control for Networks on Chip.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

QoS aware BiNoC architecture.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

2009
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Performance-energy tradeoffs in reliable NoCs.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Fluidity concept for NoC: A congestion avoidance and relief routing scheme.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Flow Maximization for NoC Routing Algorithms.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008


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