Yiming Ouyang

Orcid: 0000-0003-2759-8754

According to our database1, Yiming Ouyang authored at least 62 papers between 2012 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Traffic-oriented reconfigurable NoC with augmented inter-port buffer sharing.
Frontiers Inf. Technol. Electron. Eng., October, 2024

DBU-PG: energy-efficient noc design using dual-buffering power gating.
J. Supercomput., July, 2024

Ti3D-contact, a high-resolution and whole-body dataset of hand-object contact area based on 3D scanning method.
Dataset, June, 2024

Fault-tolerant routing for reliable packet transmission in on-chip networks.
Microelectron. J., 2024

A tree-recursive partitioned multicast mechanism for NoC-based deep neural network accelerator.
Microelectron. J., 2024

SPONGE+: A NoC-based power gating scheme for overall router column opening and closing control.
Microelectron. J., 2024

A lightweight reversible multi-mode physical unclonable function.
Microelectron. J., 2024

Design of radiation hardened latch with low delay and tolerance of quadruple-node-upset in 32 nm process.
Microelectron. J., 2024

Applying SMART-Based Power Gating Approach in NoC System.
J. Circuits Syst. Comput., 2024

A fast hardware accelerator for nighttime fog removal based on image fusion.
Integr., 2024

Self-Supervised Alignment Learning For Medical Image Segmentation.
Proceedings of the IEEE International Symposium on Biomedical Imaging, 2024

2023
RMC_NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

Improving power and performance of on-chip network through virtual channel sharing and power gating.
Integr., November, 2023

A soft-packaged and portable rehabilitation glove capable of closed-loop fine motor skills.
Nat. Mac. Intell., October, 2023

URMP: using reconfigurable multicast path for NoC-based deep neural network accelerators.
J. Supercomput., September, 2023

Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets.
J. Electron. Test., June, 2023

Dynamic detection of wireless interface faults and fault-tolerant routing algorithm in WiNoC.
Integr., May, 2023

Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023

An Area-Efficient Large Integer NTT-Multiplier Using Discrete Twiddle Factor Approach.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

Transit ring: bubble flow control for eliminating inter-ring communication congestion.
J. Supercomput., 2023

A transparent virtual channel power gating method for on-chip network routers.
Integr., 2023

2022
Pitstop++: Enabling stable and fair deadlock freedom on fault-tolerant NoC.
Microprocess. Microsystems, October, 2022

A router architecture with dual input and dual output channels for Networks-on-Chip.
Microprocess. Microsystems, April, 2022

DCBuf: a high-performance wireless network-on-chip architecture with distributed wireless interconnects and centralized buffer sharing.
Wirel. Networks, 2022

REE: Reconfigurable and energy-efficient router architecture in wireless network-on-chip.
Microelectron. J., 2022

Design of fully adaptive routing and hybrid VC allocation in wireless NOC.
Microelectron. J., 2022

Architecting a congestion pre-avoidance and load-balanced wireless network-on-chip.
J. Parallel Distributed Comput., 2022

2021
MMNNN: A tree-based Multicast Mechanism for NoC-based deep Neural Network accelerators.
Microprocess. Microsystems, September, 2021

Architecting a priority-based dynamic media access control mechanism in Wireless Network-on-Chip.
Microelectron. J., 2021

A high-speed and triple-node-upset recovery latch with heterogeneous interconnection.
Microelectron. J., 2021

Design of MNU-Resilient latches based on input-split C-elements.
Microelectron. J., 2021

Design of node separated triple-node-upset self-recoverable latch.
Microelectron. J., 2021

Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems.
J. Electron. Test., 2021

Shape and Force Sensing of A Soft SMA Planar Actuator for Soft Robots.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2021

2020
A low-latency DMM-1 encoder for 3D-HEVC.
J. Real Time Image Process., 2020

Design of a Wireless Router with Virtual Channel Fault Tolerant in WiNoC.
J. Circuits Syst. Comput., 2020

cm<sup>3</sup>WiNoCs: Congestion-Aware Millimeter-Wave Multichannel Wireless Networks-on-Chip.
IEEE Access, 2020

A Novel Low-Latency Regional Fault-Aware Fault-Tolerant Routing Algorithm for Wireless NoC.
IEEE Access, 2020

2019
SSS: Self-aware System-on-chip Using a Static-dynamic Hybrid Method.
ACM J. Emerg. Technol. Comput. Syst., 2019

Design of Wireless Network on Chip with Priority-Based MAC.
J. Circuits Syst. Comput., 2019

CPCA: An efficient wireless routing algorithm in WiNoC for cross path congestion awareness.
Integr., 2019

DVFS Based Error Avoidance Strategy in Wireless Network-on-Chip.
J. Electron. Test., 2019

Efficient Softmax Hardware Architecture for Deep Neural Networks.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Design of Low-Power WiNoC with Congestion-Aware Wireless Node.
J. Circuits Syst. Comput., 2018

An improved communication scheme for non-HOL-blocking wireless NoC.
Integr., 2018

Dynamic Fine-Grain Power Gating Design in WiNoC.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches.
IEEE Trans. Computers, 2017

Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS.
Microelectron. J., 2017

A TSV Fault-Tolerant Scheme Based on Failure Classification in 3D-NoC.
J. Circuits Syst. Comput., 2017

A highly reliable butterfly PUF in SRAM-based FPGAs.
IEICE Electron. Express, 2017

On the Accuracy of Stochastic Delay Bound for Network on Chip.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

SSS: self-aware system-on-chip using static-dynamic hybrid method (work-in-progress).
Proceedings of the 2017 International Conference on Compilers, 2017

2016
An SEU resilient, SET filterable and cost effective latch in presence of PVT variations.
Microelectron. Reliab., 2016

AFTER: Asynchronous Fault-Tolerant Router Design in Network-on-Chip.
J. Circuits Syst. Comput., 2016

Thread Progress Aware Block Migration for Dynamic NUCA.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

2015
Cost-aware demand scheduling for delay tolerant applications.
J. Netw. Comput. Appl., 2015

2014
Optimized stacking order for 3D-stacked ICs considering the probability and cost of failed bonding.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

CR5M: A mirroring-powered channel-RAID5 architecture for an SSD.
Proceedings of the IEEE 30th Symposium on Mass Storage Systems and Technologies, 2014

2013
PDB: A Reliability-Driven Data Reconstruction Strategy Based on Popular Data Backup for RAID4 SSD Arrays.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

SPD-RAID4: Splitting Parity Disk for RAID4 Structured Parallel SSD Arrays.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

2012
Making Garbage Collection Wear Conscious for Flash SSD.
Proceedings of the Seventh IEEE International Conference on Networking, 2012


  Loading...