Yikui Dong
According to our database1,
Yikui Dong
authored at least 7 papers
between 2001 and 2024.
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Bibliography
2024
A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2013
A self-calibrating multi-VCO PLL scheme with leakage and capacitive modulation mitigations.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2011
A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS.
IEEE J. Solid State Circuits, 2011
A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001