Yijun Cui
Orcid: 0000-0002-6262-2329Affiliations:
- Nanjing University of Aeronautics and Astronautics, Jiangsu, China
According to our database1,
Yijun Cui
authored at least 35 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
ACM Trans. Design Autom. Electr. Syst., January, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
How Practical Phase-Shift Errors Affect Beamforming of Reconfigurable Intelligent Surface?
IEEE Trans. Commun., October, 2023
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
Dynamic self-test scheme and authentication protocol for improving robustness of strong PUF.
Microelectron. J., September, 2023
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
An Efficient Hardware Accelerator of High-Speed NTT for CRYSTALS-Kyber Post-Quantum Cryptography.
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023
2022
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Emerg. Top. Comput., 2022
Simulation and Field Trial Results of Reconfigurable Intelligent Surfaces in 5G Networks.
IEEE Access, 2022
A Novel Combined Correlation Power Analysis (CPA) Attack on Schoolbook Polynomial Multiplication in Lattice-based Cryptosystems.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Horizontal Correlation Analysis without Precise Location on Schoolbook Polynomial Multiplication of Lattice-based Cryptosystem.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Lightweight and Efficient Hardware Implementation for Saber Using NTT Multiplication.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation.
IEEE Trans. Emerg. Top. Comput., 2021
Secur. Commun. Networks, 2021
A lightweight key renewal scheme based authentication protocol with configurable RO PUF for clustered sensor networks.
Microelectron. J., 2021
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design.
IEEE Access, 2018
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Live demonstration: An automatic evaluation platform for physical unclonable function test.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEICE Electron. Express, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015