Yihua Huang

Orcid: 0000-0001-6736-7913

Affiliations:
  • Sun Yat-Sen University, School of Electronic and Information Technology, Guangzhou, China


According to our database1, Yihua Huang authored at least 19 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
Re-HGNM: a repeat aware hypergraph neural machine for session-based recommendation.
Neural Comput. Appl., 2024

HR-GCN: An Efficient GCN Accelerator for Heterogeneous Graph Data and R-GCN Model.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

SpGCN: An FPGA-Based Graph Convolutional Network Accelerator for Sparse Graphs.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

A Novel FPGA Accelerator of R(2+1)D.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

MRH-GCN: An Efficient GCN Accelerator for Multi-Relation Heterogeneous Graph.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

2023
The Learnable Model-Based Genetic Algorithm for the IP Mapping Problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

BSTMSM: A High-Performance FPGA-based Multi-Scalar Multiplication Hardware Accelerator.
Proceedings of the International Conference on Field Programmable Technology, 2023

A Novel Hardware Accelerator of NeRF Based on Xilinx UltraScale and UltraScale+ FPGA.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

2022
FPGA-Based High-Throughput CNN Hardware Accelerator With High Computing Resource Utilization Ratio.
IEEE Trans. Neural Networks Learn. Syst., 2022

Hardware Design and Implementation of Post-Quantum Cryptography Kyber.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

A High-performance Deployment Framework for Pipelined CNN Accelerators with Flexible DSE Strategy.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

Hardware Design and Implementation of Classic McEliece Post-Quantum Cryptosystem Based on FPGA.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

TFR-GCN: A GCN Accelerator with Tile-Fusing Strategy.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2021
An IP Core Mapping Algorithm Based on Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A Reinforcement Learning-Based Framework for Solving the IP Mapping Problem.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2020
Deep Convolutional Neural Networks-Based Automatic Breast Segmentation and Mass Detection in DCE-MRI.
Comput. Math. Methods Medicine, 2020

A Tag Based Random Order Vector Reduction Circuit.
IEEE Access, 2020

A Hybrid-Pipelined Architecture for FPGA-based Binary Weight DenseNet with High Performance-Efficiency.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2019
Implementation and Area Optimization of LUT6 Based Convolution Structure on FPGA.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019


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