Yihe Sun

According to our database¹, Yihe Sun authored at least 31 papers between 2001 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

Low/Middle-Frequency Positive External- Damping Design Under Self-Stability Constraint for Inner Control Loop of Grid-Forming Converters.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., May, 2024

2013

Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Eng., 2013

2012

Reliability Modeling and Management of Nanophotonic On-Chip Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

2011

MOPED: Accelerating Data Communication on Future CMPs.

[BibT_eX]

[DOI]

IEEE Micro, 2011

Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

MOPED: Orchestrating interprocess message data on CMPs.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Memory efficient on-line streaming for multichannel spike train analysis.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Real-time neuronal networks reconstruction using hierarchical systolic arrays.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Feasibility study for future implantable neural-silicon interface devices.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

2010

Global On-Chip Coordination at Light Speed.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2010

Power-efficient variation-aware photonic on-chip network management.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Accelerating data movement on future chip multi-processors.

[BibT_eX]

[DOI]

Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies, 2010

A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009

A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures.

[BibT_eX]

[DOI]

Yang Xu

Hu He

Yihe Sun

J. Low Power Electron., 2009

A high-performance low-power nanophotonic on-chip network.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism.

[BibT_eX]

[DOI]

Zheng Shen

Hu He

Yihe Sun

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Latency criticality aware on-chip communication.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Spectrum: a hybrid nanophotonic-electric on-chip network.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Transaction-Aware Network-on-Chip Resource Reservation.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2008

Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007

A Video Specific Instruction Set Architecture for ASIP design.

[BibT_eX]

[DOI]

VLSI Design, 2007

Heuristic on a Novel Power Management System Cooperating with Compiler.

[BibT_eX]

[DOI]

J. Low Power Electron., 2007

A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2006), 2006

A Retargetable Compiler of VLIW ASIP for Media Signal Processing.

[BibT_eX]

Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

2005

A new register file access architecture for software pipelining in VLIW processors.

[BibT_eX]

[DOI]

Yanjun Zhang

Hu He

Yihe Sun

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003

A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2003

Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST.

[BibT_eX]

[DOI]

He Hu

Yihe Sun

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

An Optimizing Search Method of Systolic Array Design.

[BibT_eX]

Ke Jiang

Yihe Sun

Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

2001

Scan array solution for testing power and testing time.

[BibT_eX]

[DOI]

Lei Xu

Yihe Sun

Hongyi Chen

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Yihe Sun

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...