Yih Wang
Orcid: 0000-0002-4580-2870
According to our database1,
Yih Wang
authored at least 34 papers
between 2005 and 2024.
Collaborative distances:
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Bibliography
2024
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024
A 3.3GHz 1024X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 10<sup>12</sup> Write Endurance and Integrated Margin-Expansion Schemes.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm<sup>2</sup> Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm<sup>2</sup> and 3.78Mb/mm<sup>2</sup> Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2023
Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 5-nm 254-TOPS/W 221-TOPS/mm<sup>2</sup> Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS.
IEEE J. Solid State Circuits, 2021
A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
An 89TOPS/W and 16.3TOPS/mm<sup>2</sup> All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2015
IEEE J. Solid State Circuits, 2015
2014
2<sup>nd</sup> generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology.
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry.
IEEE J. Solid State Circuits, 2013
2012
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation.
IEEE J. Solid State Circuits, 2011
IEEE Des. Test Comput., 2011
2010
A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management.
IEEE J. Solid State Circuits, 2010
A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits.
IEEE J. Solid State Circuits, 2009
A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology.
IEEE J. Solid State Circuits, 2009
A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.
IEEE J. Solid State Circuits, 2008
A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply.
IEEE J. Solid State Circuits, 2006
2005
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction.
IEEE J. Solid State Circuits, 2005