Yici Cai
Affiliations:- Tsinghua University, Department of Computer Science and Technology, Beijing, China
- University of Science and Technology of China, Hefei, China (PhD 2007)
According to our database1,
Yici Cai
authored at least 249 papers
between 1999 and 2023.
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Bibliography
2023
IEEE Trans. Very Large Scale Integr. Syst., November, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Proceedings of the 26th International Conference on Pattern Recognition, 2022
2021
Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Temperature-Aware Electromigration Analysis with Current-Tracking in Power Grid Networks.
J. Comput. Sci. Technol., 2021
CCF Trans. High Perform. Comput., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
SRL: Separation-and-Recombination Learning for Video Facial Landmark Detection with Limited Data.
Proceedings of the 16th IEEE International Conference on Automatic Face and Gesture Recognition, 2021
2020
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2019
Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding.
Integr., 2019
Integr., 2019
Comput. Graph., 2019
Composite Optimization for Electromigration Reliability and Noise in Power Grid Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
J. Comput. Sci. Technol., 2018
Poet-based Poetry Generation: Controlling Personal Style with Recurrent Neural Networks.
Proceedings of the 2018 International Conference on Computing, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Biomed. Circuits Syst., 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 2017 IEEE International Congress on Big Data, 2017
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths.
J. Comput. Sci. Technol., 2015
J. Comput. Sci. Technol., 2015
IEEE Des. Test, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015
PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Microelectron. J., 2014
J. Comput. Sci. Technol., 2014
Integr., 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Power supply noise aware evaluation framework for side channel attacks and countermeasures.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Fast vectorless power grid verification using maximum voltage drop location estimation.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Time-domain performance bound analysis for analog and interconnect circuits considering process variations.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013
Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013
A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
A novel fine-grain track routing approach for routability and crosstalk optimization.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 2011 15th International Conference on Computer Supported Cooperative Work in Design, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Variational Capacitance Extraction and Modeling Based on Orthogonal Polynomial Method.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.
Integr., 2010
Integr., 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 2010 14th International Conference on Computer Supported Cooperative Work in Design, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Sci. China Ser. F Inf. Sci., 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Decoupling capacitance efficient placement for reducing transient power supply noise.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009
Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.
Integr., 2008
Integr., 2008
IET Circuits Devices Syst., 2008
Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Sci. China Ser. F Inf. Sci., 2008
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 2008 International Symposium on Physical Design, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 26th International Conference on Computer Design, 2008
A novel performance driven power gating based on distributed sleep transistor network.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.
Proceedings of the FPL 2008, 2008
Low power clock buffer planning methodology in F-D placement for large scale circuit design.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Integr., 2007
Partitioning-based decoupling capacitor budgeting via sequence of linear programming.
Integr., 2007
Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Statistical model order reduction for interconnect circuits considering spatial correlations.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
J. Comput. Sci. Technol., 2006
Sci. China Ser. F Inf. Sci., 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
High accurate pattern based precondition method for extremely large power/ground grid analysis.
Proceedings of the 2006 International Symposium on Physical Design, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
J. Comput. Sci. Technol., 2005
Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain.
J. Comput. Sci. Technol., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Sci. China Ser. F Inf. Sci., 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the Integrated Circuit and System Design, 2005
A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design.
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Zero skew clock routing with tree topology construction using simulated annealing method.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A global interconnect optimization algorithm under accurate delay model using solution space smoothing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem.
Proceedings of the Advances in Natural Computation, First International Conference, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Stairway compaction using corner block list and its applications with rectilinear blocks.
ACM Trans. Design Autom. Electr. Syst., 2004
IEEE Trans. Circuits Syst. II Express Briefs, 2004
Area minimization of power distribution network using efficient nonlinear programming techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Sci. China Ser. F Inf. Sci., 2004
Sci. China Ser. F Inf. Sci., 2004
Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.
Proceedings of the Integrated Circuit and System Design, 2004
Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Quick and effective buffered legitimate skew clock routing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Shielding area optimization under the solution of interconnect crosstalk.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Crosstalk driven routing resource assignment.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Algorithm for yield driven correction of layout.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Layer assignment algorithm for RLC crosstalk minimization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
J. Comput. Sci. Technol., 2003
Integr., 2003
A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Proceedings of the 2003 International Symposium on Physical Design, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Dynamic global buffer planning optimization based on detail block locating and congestion analysis.
Proceedings of the 40th Design Automation Conference, 2003
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
J. Comput. Sci. Technol., 2002
A multi-step standard-cell placement algorithm of optimizing timing and congestion behavior.
Sci. China Ser. F Inf. Sci., 2002
A novel and efficient timing-driven global router for standard cell layout design based on critical network concept.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of ASP-DAC 2001, 2001
Proceedings of ASP-DAC 2001, 2001
2000
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
MMP: a novel placement algorithm for combined macro block and standard cell layout design.
Proceedings of ASP-DAC 2000, 2000
Proceedings of ASP-DAC 2000, 2000
1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999