Yibo Wang

According to our database, Yibo Wang authored at least 7 papers between 2005 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation.

Yibo Wang, Yici Cai, Xianlong Hong

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Symmetry constraint based on mismatch analysis for analog layout in SOI technology.

Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration.

Yibo Wang, Yici Cai, Xianlong Hong, Yi Zou

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

Performance and power aware buffered tree construction.

Yibo Wang, Yici Cai, Xianlong Hong

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A novel technique integrating buffer insertion into timing driven placement.

Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model.

Yibo Wang, Yici Cai, Xianlong Hong

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A global interconnect optimization algorithm under accurate delay model using solution space smoothing.

Yici Cai, Yibo Wang, Xianlong Hong

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005