Yibo Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

A GPU-Accelerated Framework for Path-Based Timing Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

DREAMPlace 4.0: Timing-Driven Placement With Momentum-Based Net Weighting and Lagrangian-Based Refinement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., September, 2023

FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Introduction to the Special Issue on Machine Learning for CAD/EDA.

[BibT_eX]

[DOI]

Avi Ziv

Haoxing Ren

ACM Trans. Design Autom. Electr. Syst., March, 2023

Interactive Analog Layout Editing With Instant Placement and Routing Legalization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

Efficient Aging-Aware Standard Cell Library Characterization Based on Sensitivity Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration.

[BibT_eX]

[DOI]

CoRR, 2023

HybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Prediction.

[BibT_eX]

[DOI]

CoRR, 2023

Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization.

[BibT_eX]

[DOI]

CoRR, 2023

Khronos: Fusing Memory Access for Improved Hardware RTL Simulation.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract).

[BibT_eX]

[DOI]

Proceedings of the Thirty-Second International Joint Conference on Artificial Intelligence, 2023

READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Stronger Mixed-Size Placement Backbone Considering Second-Order Information.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Mitigating Distribution Shift for Congestion Optimization in Global Placement.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

On a Moreau Envelope Wirelength Model for Analytical Global Placement.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

A Robust FPGA Router with Concurrent Intra-CLB Rerouting.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Taskflow: A Lightweight Parallel and Heterogeneous Task Graph Computing System.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2022

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Asynchronous Reinforcement Learning Framework and Knowledge Transfer for Net-Order Exploration in Detailed Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Adaptive Layout Decomposition With Graph Embedding Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview.

[BibT_eX]

[DOI]

CoRR, 2022

Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++.

[BibT_eX]

[DOI]

CoRR, 2022

CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA).

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2022

Efficient Design Rule Checking Script Generation via Key Information Extraction.

[BibT_eX]

[DOI]

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

A Tale of EDA's Long Tail: Long-Tailed Distribution Learning for Electronic Design Automation.

[BibT_eX]

[DOI]

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

Concurrent CPU-GPU Task Programming using Modern C++.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

GPU-Accelerated Rectilinear Steiner Tree Generation.

[BibT_eX]

[DOI]

Feng Gu

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

DREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net Weighting.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

LHNN: lattice hypergraph neural network for VLSI congestion prediction.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

A timing engine inspired graph neural network model for pre-routing slack prediction.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Differentiable-timing-driven global placement.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Efficient Critical Paths Search Algorithm using Mergeable Heap.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

FPGA-Accelerated Maze Routing Kernel for VLSI Designs.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

OpenMPL: An Open-Source Layout Decomposer.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

Asynchronous Multi-Nets Detailed Routing in VLSI using Multi-Agent Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International Conference on Network Intelligence and Digital Content, 2021

GPU-accelerated Critical Path Generation with Path Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Global Placement with Deep Learning-Enabled Explicit Routability Optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Towards AQFP-Capable Physical Design Automation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Ultrafast CPU/GPU Kernels for Density Accumulation in Placement.

[BibT_eX]

[DOI]

Jing Mai

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

GPU-accelerated Path-based Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Interactive Analog Layout Editing with Instant Placement Legalization.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Deep Learning for Mask Synthesis and Verification: A Survey.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Physical Synthesis for Advanced Neural Network Processors.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Semisupervised Hotspot Detection With Self-Paced Multitask Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Cpp-Taskflow v2: A General-purpose Parallel and Heterogeneous Task Programming System at Scale.

[BibT_eX]

[DOI]

CoRR, 2020

Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks.

[BibT_eX]

[DOI]

Jing Chen

IEEE Access, 2020

TEMPO: Fast Mask Topography Effect Modeling with Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

GPU Acceleration in VLSI Back-end Design: Overview and Case Studies.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

GPU-Accelerated Static Timing Analysis.

[BibT_eX]

[DOI]

Rachel Selina Rajarathnam

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist.

[BibT_eX]

[DOI]

Yier Jin

Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

Adaptive Layout Decomposition with Graph Embedding Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

S<sup>3</sup>DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

High-Definition Routing Congestion Prediction for Large-Scale FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Device Layer-Aware Analytical Placement for Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Symposium on Physical Design, 2019

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Wuxi Li

Proceedings of the International Conference on Computer-Aided Design, 2019

Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection.

[BibT_eX]

[DOI]

Meng Li

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

LithoROC: lithography hotspot detection with explicit ROC optimization.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Tackling signal electromigration with learning-based detection and multistage mitigation.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Semi-supervised hotspot detection with self-paced multi-task learning.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

OpenMPL: An Open Source Layout Decomposer: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Towards a Theoretical Understanding of Hashing-Based Neural Nets.

[BibT_eX]

[DOI]

Zhao Song

Lin F. Yang

Proceedings of the 22nd International Conference on Artificial Intelligence and Statistics, 2019

2018

UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

Subresolution Assist Feature Generation With Supervised Data Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.

[BibT_eX]

[DOI]

Natarajan Viswanathan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

OpenMPL: An Open Source Layout Decomposer.

[BibT_eX]

[DOI]

CoRR, 2018

Machine Learning for Yield Learning and Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Physical Design, 2018

Learning Long Term Dependencies via Fourier Recurrent Units.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Machine Learning, 2018

Layout-dependent aging mitigation for critical path timing.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Redundant Local-Loop Insertion for Unidirectional Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints.

[BibT_eX]

[DOI]

Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Stitch aware detailed placement for multiple E-beam lithography.

[BibT_eX]

[DOI]

Integr., 2017

DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Placement mitigation techniques for power grid electromigration.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Patterning Aware Design Optimization of Selective Etching in N5 and Beyond.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Concurrent Pin Access Optimization for Unidirectional Routing.

[BibT_eX]

[DOI]

Xiaoqing Xu

Vinicius S. Livramento

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Design for manufacturability and reliability in extreme-scaling VLSI.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2016

A novel unified dummy fill insertion framework with SQP-based optimization method.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Pushing multiple patterning in sub-10nm: are we ready?

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2010

The Daktari: An interactive, multi-media tool for knowledge transfer among poor livestock keepers in Kenya.

[BibT_eX]

[DOI]

Comput. Educ., 2010

2009

Addressing Animal Health Knowledge Gaps in Southern Countries: The Creation of a 2D Animal Health Resource Room.

[BibT_eX]

[DOI]

Claire Heffernan

Electron. J. Inf. Syst. Dev. Ctries., 2009

Creating a mobile-phone based geographic surveillance system for avian influenza.

[BibT_eX]

[DOI]