Yi Zhang
Orcid: 0000-0003-2888-4736Affiliations:
- Tokyo Institute of Technology, Department of Electrical and Electronic Engineering, Japan
According to our database1,
Yi Zhang
authored at least 17 papers
between 2020 and 2024.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2024
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter.
IEEE J. Solid State Circuits, April, 2024
A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station.
IEEE J. Solid State Circuits, 2023
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24-71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR.
IEEE J. Solid State Circuits, 2022
A 39-GHz CMOS Bi-Directional Doherty Phased-Array Beamformer Using Shared-LUT DPD with Inter-Element Mismatch Compensation Technique for 5G Base-Station.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the 2022 IEEE 33rd Annual International Symposium on Personal, 2022
A Power-Efficient 24-to-71 GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 28GHz Area-Efficient CMOS Vector-Summing Phase Shifter Utilizing Phase-Inverting Type-I Poly-Phase Filter for 5G New Radio.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems.
IEEE J. Solid State Circuits, 2021
A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-Cancellation.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array Transceiver.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020