Yi Zhang
Orcid: 0000-0002-2690-4601Affiliations:
- Maxim Integrated, Beaverton, OR, USA
- Analog Devices, Wilmington, MA, USA (2016 - 2018)
- Oregon State University, Corvallis, OR, USA (PhD 2016)
- NXP Semiconductors, Shanghai, China (2010 - 2012)
According to our database1,
Yi Zhang
authored at least 24 papers
between 2014 and 2021.
Collaborative distances:
Collaborative distances:
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Bibliography
2021
A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
A 16 b Multi-Step Incremental Analog-to-Digital Converter With Single-Opamp Multi-Slope Extended Counting.
IEEE J. Solid State Circuits, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
A 35µW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
An incremental analog-to-digital converter with multi-step extended counting for sensor interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD Compensation and FIR Feedback.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE J. Solid State Circuits, 2015
Incremental Analog-to-Digital Converters for High-Resolution Energy-Efficient Sensor Interfaces.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 16-bit 1KHz bandwidth micro-power multi-step incremental ADC for multi-channel sensor interface.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
A continuous-time ΔΣ modulator with a digital technique for excess loop delay compensation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
A 1 V 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014