Yi-Shing Chang

Orcid: 0000-0002-9747-2586

According to our database1, Yi-Shing Chang authored at least 22 papers between 1992 and 2020.

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Bibliography

2020
Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
A Comprehensive Electro-Optical Model for Silicon Photonic Switches.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2008
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs.
J. Electron. Test., 2008

An Industrial Case Study of Sticky Path-Delay Faults.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

On Accelerating Path Delay Fault Simulation of Long Test Sequences.
Proceedings of the 2008 IEEE International Test Conference, 2008

Efficient Selection of Observation Points for Functional Tests.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2006
A Study of Implication Based Pseudo Functional Testing.
Proceedings of the 2006 IEEE International Test Conference, 2006

An Approach to Minimizing Functional Constraints.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
On modeling crosstalk faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Transition Tests for High Performance Microprocessors.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2004
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit.
Proceedings of the 2004 Design, 2004

2003
Test Generation for Maximizing Ground Bounce Considering Circuit Delay.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

On Modeling Cross-Talk Faults.
Proceedings of the 2003 Design, 2003

2001
Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

1999
Test Generation for Ground Bounce in Internal Logic Circuitry.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

1997
Analysis of Ground Bounce in Deep Sub-Micron Circuits.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

1992
Design of Concurrent Error-Detectable VLSI-Based Array Dividers.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992


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