Yi Sheng Chong
Orcid: 0000-0003-4136-6570
According to our database1,
Yi Sheng Chong
authored at least 15 papers
between 2020 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications.
Proceedings of the 36th IEEE Hot Chips Symposium, 2024
2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Recovering Accuracy of RRAM-based CIM for Binarized Neural Network via Chip-in-the-loop Training.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
0.08mm<sup>2</sup> 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
An Energy-Efficient Convolution Unit for Depthwise Separable Convolutional Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Area and Energy Efficient 2D Max-Pooling For Convolutional Neural Network Hardware Accelerator.
Proceedings of the 46th Annual Conference of the IEEE Industrial Electronics Society, 2020