Yi Sheng Chong

Orcid: 0000-0003-4136-6570

According to our database1, Yi Sheng Chong authored at least 15 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Quantum Readout Processing Accelerator with a CORDIC Core at Cryogenic Temperature.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications.
Proceedings of the 36th IEEE Hot Chips Symposium, 2024

2023
A 110nW Always-on Keyword Spotting Chip using Spiking CNN in 40nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

4b/4b/8b Precision Charge-Domain 8T-SRAM Based CiM for CNN Processing.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Noise-Aware and Lightweight LSTM for Keyword Spotting Applications.
Proceedings of the 19th International SoC Design Conference, 2022

Recovering Accuracy of RRAM-based CIM for Binarized Neural Network via Chip-in-the-loop Training.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

0.08mm<sup>2</sup> 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A Low-Cost High-Throughput Digital Design of Biorealistic Spiking Neuron.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Efficient Implementation of Activation Functions for LSTM accelerators.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

An Energy-Efficient Convolution Unit for Depthwise Separable Convolutional Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Area and Energy Efficient 2D Max-Pooling For Convolutional Neural Network Hardware Accelerator.
Proceedings of the 46th Annual Conference of the IEEE Industrial Electronics Society, 2020


  Loading...