Yi Shen

According to our database, Yi Shen authored at least 39 papers between 2014 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Rapid digital background calibration of bit weights in pipelined SAR ADC based on multi-PN injection.

Le Chen, Yi Shen, Ruixue Ding, Shubin Liu, Haolin Han

Microelectron. J., 2025

2024

A 182.9-dB FoM 108.2-dB SFDR Power/Bandwidth Configurable Fully Dynamic Switched-Capacitor Zoom ADC With Interstage Leakage Shaping.

Yuke Shen, Shubin Liu, Kui Wen, Yanbo Zhang, Yi Shen, Ruixue Ding, Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024

A Wideband Input Buffer Based on Cascade Complementary Source Follower.

Dengquan Li, Tian Feng, Jiale Ding, Yi Shen, Shubin Liu, Zhangming Zhu

IEEE Trans. Very Large Scale Integr. Syst., May, 2024

A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC.

Haolin Han, Shubin Liu, Hongzhi Liang, Yi Shen, Jianyu Guo, Ruili Ren, Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

A High Accuracy and Bandwidth Digital Background Calibration Technique for Timing Skew in TI-ADCs.

Li Dang, Shubin Liu, Ruixue Ding, Yi Shen, Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error.

Hongzhi Liang, Shubin Liu, Ruixue Ding, Yi Shen, Dengquan Li, Zhangming Zhu

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A 14b 180MS/s Pipeline-SAR ADC With Adaptive-Region-Selection Technique and Gain Error Calibration.

Junyan Hao, Yi Shen, Jin Zhang, Yanbo Zhang, Shubin Liu, Zhangming Zhu

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm.

Dengquan Li, Longsheng Wang, Yi Shen, Shubin Liu, Zhangming Zhu

IEEE Trans. Instrum. Meas., 2024

Power-efficient 12-bit 800 MS/s voltage-time hybrid domain ADC with split TDC in 28 nm CMOS.

Yun Li, Yi Shen, Yue Cao, Mengtong Wu, Li Dang, Shubin Liu, Ruixue Ding, Zhangming Zhu

Microelectron. J., 2024

A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique.

Haolin Han, Jinwei Zhang, Ruili Ren, Yi Shen, Shubin Liu, Ruixue Ding

Microelectron. J., 2024

A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry.

Haolin Han, Ruili Ren, Yi Shen, Ruixue Ding, Shubin Liu, Hongzhi Liang

Microelectron. J., 2024

2023

An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC.

Xin Zhao, Dengquan Li, Feida Wang, Yi Shen, Shubin Liu, Ruixue Ding, Zhangming Zhu

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain.

Yi Shen, Junyan Hao, Shubin Liu, Zeshuai An, Dengquan Li, Ruixue Ding, Zhangming Zhu

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS.

Dengquan Li, Xin Zhao, Yi Shen, Shubin Liu, Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

An offset and gain error calibration method in high-precision SAR ADCs.

Junyan Hao, Yi Shen, Angyang Li, Min Wang, Qing Zou, Zheng Qiu, Shubin Liu, Zhangming Zhu

Microelectron. J., September, 2023

An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique.

Yi Shen, Jian Liu, Chenxi Han, Angyang Li, Shubin Liu, Ruixue Ding, Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC.

Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Xingyuan Tong, Nan Sun

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage.

Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A $142.8-\mu \text{W}$ 98.1dB-SNDR Power/Bandwidth Configurable Fully Dynamic Discrete-Time Zoom ADC with Interstage Leakage Shaping.

Yuke Shen, Shubin Liu, Kui Wen, Yanbo Zhang, Yi Shen, Ruixue Ding, Zhangming Zhu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step.

Hongzhi Liang, Yi Shen, Jun Chang, Shubin Liu, Ruixue Ding, Zhangming Zhu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022

A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs.

Dengquan Li, Lei Zhao, Longsheng Wang, Yi Shen, Zhangming Zhu

IEEE Trans. Very Large Scale Integr. Syst., 2022

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques.

Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation.

Yi Shen, Xiyuan Tang, Xin Xin, Shubin Liu, Zhangming Zhu, Nan Sun

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration.

Yukai Huang, Jiale Ding, Dengquan Li, Xin Zhao, Shubin Liu, Yi Shen, Zhangming Zhu

Microelectron. J., 2022

Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs.

Jiale Ding, Yukai Huang, Dengquan Li, Shubin Liu, Yi Shen, Zhangming Zhu

Circuits Syst. Signal Process., 2022

A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower.

Tian Feng, Dengquan Li, Jiale Ding, Shubin Liu, Yi Shen, Zhangming Zhu

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2020

A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier.

Shubin Liu, Haolin Han, Yi Shen, Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique.

Yi Shen, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Xin Xin, Shubin Liu, Zhangming Zhu, Visvesh Sathe, Nan Sun

IEEE J. Solid State Circuits, 2020

A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation.

Xiyuan Tang, Yi Shen, Xin Xin, Shubin Liu, Jueping Cai, Zhangming Zhu, Nan Sun

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC.

Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Nan Sun

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2019

A Two-Step ADC With a Continuous-Time SAR-Based First Stage.

Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu

IEEE J. Solid State Circuits, 2019

A 0.01mm² 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor.

Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique.

Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique.

Jingyu Wang, Shubin Liu, Yi Shen, Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC.

Yi Shen, Zhangming Zhu, Shubin Liu, Yintang Yang

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2016

A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching.

Shubin Liu, Yi Shen, Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Analysis and optimization of the two-stage pipelined SAR ADCs.

Yi Shen, Zhangming Zhu

Microelectron. J., 2016

A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS.

Yi Shen, Shubin Liu, Zhangming Zhu

Microelectron. J., 2016

2014

A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductor.

Zhangming Zhu, Zheng Qiu, Yi Shen, Yintang Yang

IET Circuits Devices Syst., 2014