Yi Shan

Orcid: 0000-0002-6513-1189

According to our database1, Yi Shan authored at least 61 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
XVDPU: A High-Performance CNN Accelerator on the Versal Platform Powered by the AI Engine.
ACM Trans. Reconfigurable Technol. Syst., June, 2024

Narrative Player: Reviving Data Narratives with Visuals.
CoRR, 2024

GraphAD: Interaction Scene Graph for End-to-end Autonomous Driving.
CoRR, 2024

A Deep Learning Image Augmentation Method for Field Agriculture.
IEEE Access, 2024

Detecting as Labeling: Rethinking LiDAR-Camera Fusion in 3D Object Detection.
Proceedings of the Computer Vision - ECCV 2024, 2024

3DSFLabelling: Boosting 3D Scene Flow Estimation by Pseudo Auto-Labelling.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024

2023
Solver-In-The-Loop Cluster Resource Management for Database-as-a-Service.
Proc. VLDB Endow., 2023

Flexible Resource Allocation for Relational Database-as-a-Service.
Proc. VLDB Endow., 2023

2022
Non-Invasive Glucose Metabolism Quantification Method Based on Unilateral ICA Image Derived Input Function by Hybrid PET/MR in Ischemic Cerebrovascular Disease.
IEEE J. Biomed. Health Informatics, 2022

Deformation and Volumetric Change in a Typical Retrogressive Thaw Slump in Permafrost Regions of the Central Tibetan Plateau, China.
Remote. Sens., 2022

Tenant Placement in Over-subscribed Database-as-a-Service Clusters.
Proc. VLDB Endow., 2022

HPS-Det: Dynamic Sample Assignment with Hyper-Parameter Search for Object Detection.
CoRR, 2022

A-U3D: A Unified 2D/3D CNN Accelerator on the Versal Platform for Disparity Estimation.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

XVDPU: A High Performance CNN Accelerator on the Versal Platform Powered by the AI Engine.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Dual Cross-Attention Learning for Fine-Grained Visual Categorization and Object Re-Identification.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

Efficient Image Super-Resolution with Collapsible Linear Blocks.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022

Dynamic Sparse R-CNN.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

Cross-Dataset Collaborative Learning for Semantic Segmentation in Autonomous Driving.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021
High-Performance Mixed-Low-Precision CNN Inference Accelerator on FPGA.
IEEE Micro, 2021

Cross-Dataset Collaborative Learning for Semantic Segmentation.
CoRR, 2021

Towards Discriminative Representation Learning for Unsupervised Person Re-identification.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

Improving Low-Precision Network Quantization via Bin Regularization.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

RankDetNet: Delving Into Ranking Constraints for Object Detection.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

2020
DNNVM: End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-Based CNN Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Design of a High-Performance Low-Cost Radiation-Hardened Phase-Locked Loop for Space Application.
IEEE Trans. Aerosp. Electron. Syst., 2020

Identifying and characterizing projections from the subthalamic nucleus to the cerebellum in humans.
NeuroImage, 2020

An Enhanced Well-Changed GGNMOS for 3.3-V ESD Protection in 0.13-µm SOI Process.
IEICE Trans. Electron., 2020

A 16 bit 200 kS/s successive approximation register ADC with foreground on-chip self-calibration.
IEICE Electron. Express, 2020

A 16-bit 8-MS/s SAR ADC with a foreground calibration and hybrid-charge-supply power structure.
IEICE Electron. Express, 2020

LPAC: A Low-Precision Accelerator for CNN on FPGAs.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

ProgressFace: Scale-Aware Progressive Learning for Face Detection.
Proceedings of the Computer Vision - ECCV 2020, 2020

Dual Super-Resolution Learning for Semantic Segmentation.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Black Box Search Space Profiling for Accelerator-Aware Neural Architecture Search.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

MTNAS: Search Multi-task Networks for Autonomous Driving.
Proceedings of the Computer Vision - ACCV 2020 - 15th Asian Conference on Computer Vision, Kyoto, Japan, November 30, 2020

Feature Variance Regularization: A Simple Way to Improve the Generalizability of Neural Networks.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020

2019
An In-depth Comparison of Compilers for Deep Neural Networks on Hardware.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

A High-Performance CNN Processor Based on FPGA for MobileNets.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A Fine-Grained Sparse Accelerator for Multi-Precision DNN.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

DNNVM: End-to-End Compiler Leveraging Operation Fusion on FPGA-based CNN Accelerators.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Multi-task ADAS system on FPGA.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
An Efficient Reconfigurable Framework for General Purpose CNN-RNN Models on FPGAs.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Real-Time Object Detection and Semantic Segmentation Hardware System with Deep Learning Networks.
Proceedings of the International Conference on Field-Programmable Technology, 2018

ADAS and Video Surveillance Analytics System Using Deep Learning Algorithms on FPGA.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
Constructing target-aware results for keyword search on knowledge graphs.
Data Knowl. Eng., 2017

Fast HEVC intra coding algorithm based on machine learning and Laplacian Transparent Composite Model.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

2016
Semantic Keyword Search on Large-Scale Semi-Structured Data.
PhD thesis, 2016

2015
RRAM-Based Analog Approximate Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Ranking Friendly Result Composition for XML Keyword Search.
Proceedings of the Conceptual Modeling - 34th International Conference, 2015

Scalable Query Optimization for Efficient Data Processing Using MapReduce.
Proceedings of the 2015 IEEE International Congress on Big Data, New York City, NY, USA, June 27, 2015

2014
Hardware Acceleration for an Accurate Stereo Vision System Using Mini-Census Adaptive Support Region.
ACM Trans. Embed. Comput. Syst., 2014

Online scheduling for FPGA computation in the Cloud.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Enabling FPGAs in the cloud.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013
Memristor-based approximated computation.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012
FPGA based memory efficient high resolution stereo vision system for video tolling.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
An Unassisted Low-Voltage-Trigger ESD Protection Structure in a 0.18-µm CMOS Process without Extra Process Cost.
IEICE Trans. Electron., 2010

FPGA and GPU implementation of large scale SpMV.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

Efficient PageRank and SpMV Computation on AMD GPUs.
Proceedings of the 39th International Conference on Parallel Processing, 2010

Making Human Connectome Faster: GPU Acceleration of Brain Network Analysis.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

FPMR: MapReduce framework on FPGA.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009
New substrate-triggered ESD protection structures in a 0.18-µm CMOS process without extra mask.
Microelectron. Reliab., 2009


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