Yi-Ping You
Orcid: 0000-0002-4455-3147
According to our database1,
Yi-Ping You
authored at least 31 papers
between 2002 and 2025.
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
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on dl.acm.org
On csauthors.net:
Bibliography
2025
ACM Trans. Cyber Phys. Syst., January, 2025
2024
Proceedings of the Workshop Proceedings of the 53rd International Conference on Parallel Processing, 2024
2023
J. Signal Process. Syst., May, 2023
Proceedings of the 52nd International Conference on Parallel Processing Workshops, 2023
2022
Reduced O3 subsequence labelling: a stepping stone towards optimisation sequence prediction.
Connect. Sci., 2022
Connect. Sci., 2022
Proceedings of the Web Information Systems Engineering - WISE 2022, 2022
Proceedings of the Workshop Proceedings of the 51st International Conference on Parallel Processing, 2022
2019
J. Syst. Archit., 2019
Proceedings of the 48th International Conference on Parallel Processing, 2019
2018
Proceedings of the 47th International Conference on Parallel Processing, 2018
2016
ACM Trans. Embed. Comput. Syst., 2016
Softw. Pract. Exp., 2016
2015
Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2015
Proceedings of the 2015 International Conference on Compilers, 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
Softw. Pract. Exp., 2014
2013
ACM Trans. Embed. Comput. Syst., 2013
2009
LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files.
Concurr. Comput. Pract. Exp., 2009
2008
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores.
J. Signal Process. Syst., 2008
2007
ACM Trans. Design Autom. Electr. Syst., 2007
Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains.
J. Supercomput., 2007
PALF: compiler supports for irregular register files in clustered VLIW DSP processors.
Concurr. Comput. Pract. Exp., 2007
Enabling compiler flow for embedded VLIW DSP processors with distributed register files.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007
2006
Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006
2005
Proceedings of the Languages and Compilers for Parallel Computing, 2005
Proceedings of the EMSOFT 2005, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the Languages and Compilers for High Performance Computing, 2004
2002
Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002