Yi-Lin Chuang

According to our database, Yi-Lin Chuang authored at least 11 papers between 2007 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Exploring the Design Space of User-System Communication for Smart-home Routine Assistants.

Yi-Shyuan Chiang, Ruei-Che Chang, Yi-Lin Chuang, Shih-Ya Chou, Hao-Ping Lee, I-Ju Lin, Jian-Hua Jiang Chen, Yung-Ju Chang

Proceedings of the CHI '20: CHI Conference on Human Factors in Computing Systems, 2020

2014

Pulsed-Latch Utilization for Clock-Tree Power Optimization.

Hong-Ting Lin, Yi-Lin Chuang, Zong-Han Yang, Tsung-Yi Ho

IEEE Trans. Very Large Scale Integr. Syst., 2014

2012

Statistical thermal modeling and optimization considering leakage power variations.

Da-Cheng Juan, Yi-Lin Chuang, Diana Marculescu, Yao-Wen Chang

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs.

Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Pulsed-Latch Aware Placement for Timing-Integrity Optimization.

Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Pulsed-latch-based clock tree migration for dynamic power reduction.

Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs.

Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

Design-hierarchy aware mixed-size placement for routability optimization.

Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2008

Effective Wire Models for X-Architecture Placement.

Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Constraint graph-based macro placement for modern mixed-size circuit designs.

Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007

X-architecture placement based on effective wire models.

Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang

Proceedings of the 2007 International Symposium on Physical Design, 2007