Yi-Jung Chen

According to our database, Yi-Jung Chen authored at least 20 papers between 2004 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2023

Tensor Movement Orchestration in Multi-GPU Training Systems.

Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022

PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support.

Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2020

Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories.

Chia-Yin Liu, Yi-Jung Chen, Masanori Hariyama

Proceedings of the SAC '20: The 35th ACM/SIGAPP Symposium on Applied Computing, online event, [Brno, Czech Republic], March 30, 2020

2018

Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memories.

Chia-Yin Liu, Cheng-En Wu, Yi-Jung Chen

Proceedings of the 2018 Conference on Research in Adaptive and Convergent Systems, 2018

2017

Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives.

Che-Wei Chang, Geng-You Chen, Yi-Jung Chen, Chia-Wei Yeh, Pei Yin Eng, Ana Cheung, Chia-Lin Yang

IEEE Trans. Computers, 2017

Processors Allocation for MPSoCs With Single ISA Heterogeneous Multi-Core Architecture.

Yi-Jung Chen, Wen-Wei Chang, Chia-Yin Liu, Cheng-En Wu, Bo-Yuan Chen, Ming-Ying Tsai

IEEE Access, 2017

2015

SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs.

Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang

ACM Trans. Archit. Code Optim., 2015

Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs.

Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu

Proceedings of the 2015 Conference on research in adaptive and convergent systems, 2015

2014

Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs.

Meng-Ling Tsai, Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs.

Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012

SECRET: Selective error correction for refresh energy reduction in DRAMs.

Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs.

Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems.

Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen

IEEE Trans. Computers, 2011

2010

PM-COSYN: PE and memory co-synthesis for MPSoCs.

Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang

Proceedings of the Design, Automation and Test in Europe, 2010

2009

An architectural co-synthesis algorithm for energy-aware Network-on-Chip design.

Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang

J. Syst. Archit., 2009

2007

Improved Modulo (2n+1) Multiplier for IDEA.

Yi-Jung Chen, Dyi-Rong Duh, Yunghsiang Sam Han

J. Inf. Sci. Eng., 2007

An architectural co-synthesis algorithm for energy-aware network-on-chip design.

Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su

Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

Cache leakage control mechanism for hard real-time systems.

Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen

Proceedings of the 2007 International Conference on Compilers, 2007

2006

Branch Behavior Characterization for Multimedia Applications.

Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen

Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2004

A New Modulo (2ⁿ+1) Multiplier for IDEA.

Yi-Jung Chen, Dyi-Rong Duh, Yunghsiang S. Han

Proceedings of the International Conference on Security and Management, 2004