Yi-Hung Yang

According to our database, Yi-Hung Yang authored at least 3 papers between 2012 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition.

Wei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, Kai-Ting Chang

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An 8 Gbps, 4: 1 transition-aware self-toggling multiplexer.

Wei-Zen Chen, Yi-Hung Yang

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2012

A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology.

Wei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, Guo-Wei Huang, Wen-De Liu, Chih-Hua Hsiao, Shu-Yu Lin, Jung Yen Liao

Proceedings of the Symposium on VLSI Circuits, 2012