Yi Hsu
According to our database1,
Yi Hsu
authored at least 4 papers
between 2009 and 2022.
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Bibliography
2022
A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2021
Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Multi-threaded System Design of A Multi-Precision Deep Learning Accelerator on FPGA with Optimized Memory Usage.
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021
2009