Yi-Hao Lan

According to our database¹, Yi-Hao Lan authored at least 3 papers in 2024.

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2024

A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., August, 2024

A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., July, 2024

A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., April, 2024