Yi Feng

According to our database, Yi Feng authored at least 6 papers between 2007 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Page policy control with memory partitioning for DRAM performance and power efficiency.

Mingli Xie, Dong Tong, Yi Feng, Kan Huang, Xu Cheng

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2010

Research Progress of UniCore CPUs and PKUnity SoCs.

Xu Cheng, Xiaoyin Wang, Junlin Lu, Jiangfang Yi, Dong Tong, Xuetao Guan, Feng Liu, Xianhua Liu, Chun Yang, Yi Feng

J. Comput. Sci. Technol., 2010

TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures.

Dan Liu, Yi Feng, Jingjin Zhou, Dong Tong, Xu Cheng, Keyi Wang

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A customized design of DRAM controller for on-chip 3D DRAM stacking.

Tao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A 3D SoC design for H.264 application with on-chip DRAM stacking.

Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Jing Xie, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2007

Clock domain crossing fault model and coverage metric for validation of SoC design.

Yi Feng, Zheng Zhou, Dong Tong, Xu Cheng

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007