Yi-Fang Chiu

According to our database, Yi-Fang Chiu authored at least 5 papers between 2001 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.

Shien-Chun Luo, Kuo-Chiang Chang, Ming-Pin Chen, Ching-Ji Huang, Yi-Fang Chiu, Po-Hsun Chen, Liang-Chia Cheng, Chih-Wei Liu, Yuan-Hua Chu

IEEE Trans. Circuits Syst. II Express Briefs, 2014

2011

Assessing e-learning 2.0 system success.

Hei-Chia Wang, Yi-Fang Chiu

Comput. Educ., 2011

2007

An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model.

Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

A Scalable Power Modeling Approach for Embedded Memory Using LIB Format.

Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2001

A high throughput 2-dimensional DCT/IDCT architecture for real-time image and video system.

Jen-Shiun Chiang, Yi-Fang Chiu, Teng-Hung Chang

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001