Yi Chen
Orcid: 0000-0002-4416-554XAffiliations:
- Nanyang Technological University, School of Electrical and Electronic Engineering, Centre of Excellence in IC Design (VIRTUS), Singapore
According to our database1,
Yi Chen
authored at least 14 papers
between 2012 and 2019.
Collaborative distances:
Collaborative distances:
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Bibliography
2019
A 2.86-TOPS/W Current Mirror Cross-Bar-Based Machine-Learning and Physical Unclonable Function Engine For Internet-of-Things Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A Current Mirror Cross Bar Based 2.86-TOPS/W Machine Learner and PUF with <2.5% BER in 65nm CMOS for IoT Application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
An Extreme Learning Machine-Based Neuromorphic Tactile Sensing System for Texture Recognition.
IEEE Trans. Biomed. Circuits Syst., 2018
2017
Current mirror array: A novel lightweight strong PUF topology with enhanced reliability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Cortical motor intention decoding on an analog co-processor with fast training for non-stationary data.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
A simultaneous neural recording and stimulation system using signal folding in recording circuits.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
IEEE Trans. Biomed. Circuits Syst., 2016
A 128-Channel Extreme Learning Machine-Based Neural Decoder for Brain Machine Interfaces.
IEEE Trans. Biomed. Circuits Syst., 2016
2015
A 128 channel 290 GMACs/W machine learning based co-processor for intention decoding in brain machine interfaces.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
2014
IEEE Trans. Biomed. Circuits Syst., 2014
2012
A digitally assisted, pseudo-resistor-less amplifier in 65nm CMOS for neural recording applications.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012