Yesh Kolla

According to our database1, Yesh Kolla authored at least 3 papers between 2010 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

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Bibliography

2016
A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range.
IEEE J. Solid State Circuits, 2016

2015
8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2010
A 45nm CMOS 13-port 64-word 41b fully associative content-addressable register file.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


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