Yeseul Jeon
Orcid: 0000-0002-5042-5504
According to our database1,
Yeseul Jeon
authored at least 14 papers
between 2018 and 2024.
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Bibliography
2024
A Robust BLE-compatible Wake-up Receiver for Ingestible Device with In-vivo Evaluation.
Proceedings of the 46th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2024
2023
A Batteryless Electrochemical Sensing System IC Based on Intra-Body Power and Data Transfer Towards Miniaturized Wearable Sensor Nodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Energy-Efficient Ingestible Drug Delivery System in the Dynamic Gastrointestinal Environment.
Proceedings of the 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2023
Proceedings of the 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2023
2022
Bayesian Shrinkage for Functional Network Models, With Applications to Longitudinal Item Response Data.
J. Comput. Graph. Stat., January, 2022
Interpretable Fusion Analytics Framework for fMRI Connectivity: Self-Attention Mechanism and Latent Space Item-Response Model.
CoRR, 2022
2021
Graph-based Trajectory Visualization for Text Mining of COVID-19 Biomedical Literature.
CoRR, 2021
IEEE Access, 2021
2019
A 100Mb/s Galvanically-Coupled Body-Channel-Communication Transceiver with 4.75pJ/b TX and 26.8 pJ/b RX for Bionic Arms.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
An Area-Efficient Rectifier with Threshold Voltage Cancellation for Intra-Body Power Transfer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Design of an On-Silicon-Interposer Passive Equalizer for Next Generation High Bandwidth Memory With Data Rate Up To 8 Gb/s.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018