Yervant Zorian

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

2007

Minimal March Tests for Detection of Dynamic Faults in Random Access Memories.

[BibT_eX]

[DOI]

J. Electron. Test., 2007

A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Making Manufacturing Work For You.

[BibT_eX]

Srikanth Venkataraman

Proceedings of the 44th Design Automation Conference, 2007

Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

2006

Guest Editors' Introduction: Big Innovations in Small Packages.

[BibT_eX]

[DOI]

Bruce C. Kim

IEEE Des. Test Comput., 2006

Session Abstract.

[BibT_eX]

[DOI]

Dennis Wassung

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Session Abstract.

[BibT_eX]

[DOI]

Bruce C. Kim

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Minimal March Tests for Dynamic Faults in Random Access Memories.

[BibT_eX]

[DOI]

Proceedings of the 11th European Test Symposium, 2006

Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Decision-making for complex SoCs in consumer electronic products.

[BibT_eX]

[DOI]

Ron Wilson

Proceedings of the 43rd Design Automation Conference, 2006

Tradeoffs and choices for emerging SoCs in high-end applications.

[BibT_eX]

[DOI]

Nic Mokhoff

Proceedings of the 43rd Design Automation Conference, 2006

2005

Guest Editors' Introduction: DFM Drives Changes in Design Flow.

[BibT_eX]

[DOI]

Juan Antonio Carballo

IEEE Des. Test Comput., 2005

Nanoscale Design & Test Challenges.

[BibT_eX]

[DOI]

Computer, 2005

SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Minimal March Tests for Unlinked Static Faults in Random Access Memories.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Optimizing SoC Manufacturability.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

IEEE 1500 utilization in SOC design and test.

[BibT_eX]

[DOI]

Avetik Yessayan

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Today's SOC test challenges.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Impact of Soft Error Challenge on SoC Design.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

On-Line Testing for Secure Implementations: Design and Validation.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark?

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Challenges in Embedded Memory Design and Test.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Choosing flows and methodologies for SoC design.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

How to determine the necessity for emerging solutions.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

T1: Design for Manufacturability.

[BibT_eX]

[DOI]

Juan Antonio Carballo

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Fault isolation for nonisolated blocks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Distributed Diagnosis of Interconnections in SoC and MCM Designs.

[BibT_eX]

[DOI]

J. Electron. Test., 2004

Guest Editors' Introduction: Design for Yield and Reliability.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2004

SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2004

Design & Test Education in Asia.

[BibT_eX]

IEEE Des. Test Comput., 2004

2003 Technology Roadmap for Semiconductors.

[BibT_eX]

[DOI]

Computer, 2004

Reducing Embedded SRAM Test Time under Redundancy Constraints.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

A Methodology for Design and Evaluation of Redundancy Allocation Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Embedded Memory Reliability: The SER Challenge.

[BibT_eX]

[DOI]

N. Derhacobian

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Investment vs. Yield Relationship for Memories in SOC.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Instruction-Based Self-Testing of Processor Cores.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Easily Testable Cellular Carry Lookahead Adders.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

IEEE CASS becomes D&T Copublisher.

[BibT_eX]

IEEE Des. Test Comput., 2003

Guest Editor's Introduction: Advances in Infrastructure IP.

[BibT_eX]

IEEE Des. Test Comput., 2003

A Hierarchical Infrastructure for SoC Test Management.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

A Test Interface for Built-In Test of Non-Isolated Scanned Cores.

[BibT_eX]

[DOI]

Sudhakar M. Reddy

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Yield Threats and Inadequacy of One-time Test.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Overview of the IEEE P1500 Standard.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Low-Cost Software-Based Self-Testing of RISC Processor Cores.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Leveraging Infrastructure IP for SoC Yield.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

On IEEE P1500's Standard for Embedded Core Test.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

2001 Technology Roadmap for Semiconductors.

[BibT_eX]

[DOI]

Alan Allan

Don Edenfeld

William H. Joyner Jr.

Andrew B. Kahng

Mike Rodgers

Computer, 2002

A March-Based Fault Location Algorithm for Static Random Access Memories.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Embedded Memory Test and Repair: Infrastructure IP for SOC Yield.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Fault Isolation Using Tests for Non-Isolated Blocks.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Effective Software Self-Test Methodology for Processor Cores.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Embedding infrastructure IP for SOC yield improvement.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

Switching activity generation with automated BIST synthesis forperformance testing of interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures.

[BibT_eX]

[DOI]

Koppolu Sasidhar

IEEE Trans. Computers, 2001

A Discussion on Test Pattern Generation for FPGA - Implemented Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2001

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths.

[BibT_eX]

[DOI]

J. Electron. Test., 2001

EIC Message.

[BibT_eX]

IEEE Des. Test Comput., 2001

Error-Free Products.

[BibT_eX]

IEEE Des. Test Comput., 2001

Huge Storage Capacity.

[BibT_eX]

IEEE Des. Test Comput., 2001

Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

An Approach for Evaluation of Redunancy Analysis Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

Testing Embedded Core-Based System Chips.

[BibT_eX]

Proceedings of the 2nd Latin American Test Workshop, 2001

IS-FPGA : a new symmetric FPGA architecture with implicit scan.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

System-on-Chip: Embedded Test Strategies.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Embedded tutorial: TRP: integrating embedded test and ATE.

[BibT_eX]

[DOI]

Carlos Eduardo Pereira

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Deterministic software-based self-testing of embedded processor cores.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

Testing the Local Interconnect Resources of SRAM-Based FPGA's.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

Wider Coverage.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2000

Embedded in this issue.

[BibT_eX]

IEEE Des. Test Comput., 2000

Flexibility and Programmability.

[BibT_eX]

IEEE Des. Test Comput., 2000

Power-/Energy Efficient BIST Schemes for Processor Data Paths.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2000

Low Power/Energy BIST Scheme for Datapaths.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Test Configuration Generation for FPGA Logic Cells.

[BibT_eX]

Proceedings of the 1st Latin American Test Workshop, 2000

Deterministic Built-In Self -Test for Shifters, Adders and ALUs in Datapaths.

[BibT_eX]

Proceedings of the 1st Latin American Test Workshop, 2000

Wrapper design for embedded core test.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

On using IEEE P1500 SECT for test plug-n-play.

[BibT_eX]

[DOI]

Rohit Kapur

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Different experiments in test generation for XILINX FPGAs.

[BibT_eX]

[DOI]

Michel Renovell

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

HD<sup>2</sup>BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Embedded-Quality for Test.

[BibT_eX]

[DOI]

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Test of Future System-on-Chips.

[BibT_eX]

[DOI]

Sujit Dey

Mike Rodgers

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Analyzing the test generation problem for an application-oriented test of FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 5th European Test Workshop, 2000

Tutorial Statement.

[BibT_eX]

[DOI]

Chris W. H. Strolenberg

Kees Veelenturf

Proceedings of the 2000 Design, 2000

Yield Improvement and Repair Trade-Off for Large Embedded Memories.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Effective Low Power BIST for Datapaths.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

System chip test: how will it impact your design?

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

TOF: a tool for test pattern generation optimization of an FPGA application oriented test.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

SoC Testing and P1500 Standard.

[BibT_eX]

[DOI]

Tsin-Yuan Chang

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

An Effective Built-In Self-Test Scheme for Parallel Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

SRAM-Based FPGAs: Testing the Embedded RAM Modules.

[BibT_eX]

[DOI]

J. Electron. Test., 1999

Integration Continues.

[BibT_eX]

IEEE Des. Test Comput., 1999

D&T Expands.

[BibT_eX]

IEEE Des. Test Comput., 1999

Focus on DRAMs.

[BibT_eX]

IEEE Des. Test Comput., 1999

Testing Embedded-Core-Based System Chips.

[BibT_eX]

[DOI]

Sujit Dey

Computer, 1999

Challenges in testing core-based system ICs.

[BibT_eX]

[DOI]

IEEE Commun. Mag., 1999

An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Towards a standard for embedded core test: an example.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study.

[BibT_eX]

[DOI]

Proceedings of the 4th European Test Workshop, 1999

Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

An Effective BIST Architecture for Fast Multiplier Cores.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Scaling Deeper to Submicron: On-Line Testing to the Rescue.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Minimizing the Number of Test Configurations for Different FPGA Families.

[BibT_eX]

[DOI]

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

On-Line Testing for VLSI - A Compendium of Approaches.

[BibT_eX]

[DOI]

Ricardo de Oliveira Duarte

J. Electron. Test., 1998

Efficient Totally Self-Checking Shifter Design.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

Challenges and Options.

[BibT_eX]

IEEE Des. Test Comput., 1998

Once Again, a Super Issue.

[BibT_eX]

IEEE Des. Test Comput., 1998

D&T: 15th Year in Service.

[BibT_eX]

IEEE Des. Test Comput., 1998

Testing the Interconnect of RAM-Based FPGAs.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1998

Effective Built-In Self-Test for Booth Multipliers.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1998

ITC 97 Panel Sessions.

[BibT_eX]

Dilip K. Bhavsar

IEEE Des. Test Comput., 1998

A D&T Roundtable: Testing Mixed Logic and DRAM Chips.

[BibT_eX]

Meh-Ron Amerian

William D. Atwell Jr.

IEEE Des. Test Comput., 1998

Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

SRAM-based FPGA's: testing the LUT/RAM modules.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

A distributed BIST technique for diagnosis of MCM interconnections.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Built in self repair for embedded high density SRAM.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Synthesis of BIST hardware for performance testing of MCM interconnections.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

High-level design validation and test.

[BibT_eX]

[DOI]

Sujit Dey

Jacob A. Abraham

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 1998

RAM-Based FPGA's: A Test Approach for the Configurable Logic.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Novel Technique for Testing FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Built-In Self-Test with an Alternating Output.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

System-Chip Test Strategies (Tutorial).

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

SRAM-Based FPGA's: Testing the Interconnect/Logic Interface.

[BibT_eX]

[DOI]

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

An Effective Multi-Chip BIST Scheme.

[BibT_eX]

[DOI]

J. Electron. Test., 1997

Fundamentals of MCM Testing and Design-for-Testability.

[BibT_eX]

[DOI]

J. Electron. Test., 1997

Guest Editorial.

[BibT_eX]

[DOI]

J. Electron. Test., 1997

Design and Test of Core-Based Systems on Chips.

[BibT_eX]

Rajesh K. Gupta

IEEE Des. Test Comput., 1997

Introducing Core-Based System Design.

[BibT_eX]

[DOI]

Rajesh K. Gupta

IEEE Des. Test Comput., 1997

Test of RAM-based FPGA: methodology and application to the interconnect.

[BibT_eX]

[DOI]

Michel Renovell

Joan Figueras

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Systems On Silicon: Design and Test Challenges.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Power Dissipation During Testing: Should We Worry About it?

[BibT_eX]

[DOI]

Hans-Joachim Wunderlich

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Test Requirements for Embedded Core-Based Systems and IEEE P1500.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

An Effective BIST Scheme for Arithmetic Logic Units.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

On the generation of pseudo-deterministic two-patterns test sequence with LFSRs.

[BibT_eX]

[DOI]

Christian Dufaza

Ricardo de Oliveira Duarte

Proceedings of the European Design and Test Conference, 1997

Fault-secure shifter design: results and implementations.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA.

[BibT_eX]

[DOI]

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

Programmable BIST Space Compactors.

[BibT_eX]

[DOI]

André Ivanov

Barry K. Tsuji

IEEE Trans. Computers, 1996

Guest Editors' Introduction: East Meets West.

[BibT_eX]

Jan Hlavicka

IEEE Des. Test Comput., 1996

Panel Summaries.

[BibT_eX]

IEEE Des. Test Comput., 1996

EIC Message.

[BibT_eX]

Kenneth D. Wagner

IEEE Des. Test Comput., 1996

Conference Reports.

[BibT_eX]

IEEE Des. Test Comput., 1996

Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates.

[BibT_eX]

[DOI]

Koppolu Sasidhar

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

An Effective BIST Scheme for Datapaths.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Designing Self-Testable Multi-Chip Modules.

[BibT_eX]

[DOI]

Proceedings of the 1996 European Design and Test Conference, 1996

Relay Propagation Scheme for Testing of MCMs on Large Area Substrates.

[BibT_eX]

[DOI]

Koppolu Sasidhar

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Integration of partial scan and built-in self-test.

[BibT_eX]

[DOI]

Chih-Jen Lin

Sudipta Bhawmik

J. Electron. Test., 1995

Conference Reports.

[BibT_eX]

IEEE Des. Test Comput., 1995

An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring.

[BibT_eX]

[DOI]

Fabian Vargas

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

An Effective BIST Scheme for Booth Multipliers.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Multi-chip module technology.

[BibT_eX]

[DOI]

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

Area versus detection latency trade-offs in self-checking memory design.

[BibT_eX]

[DOI]

O. Kebichi

Proceedings of the 1995 European Design and Test Conference, 1995

Functional test for shifting-type FIFOs.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

An effective BIST scheme for carry-save and carry-propagate array multipliers.

[BibT_eX]

[DOI]

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

Effective march algorithms for testing single-order addressed memories.

[BibT_eX]

[DOI]

J. Electron. Test., 1994

Fault models and tests for Ring Address Type FIFOs.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

An Effective BIST Scheme for Ring-Address Type FIFOs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Do You Practice Safe Tests? What We Found Out About Your Habits.

[BibT_eX]

[DOI]

Cecil A. Dean

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Functional Tests for Ring-Address SRAM-type FIFOs.

[BibT_eX]

[DOI]

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

A distributed BIST control scheme for complex VLSI devices.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

A Method for Delay Fault Self-Testing of Macrocells.

[BibT_eX]

[DOI]

Harold N. Scholz

Duane R. Aadsen