Yeonho Lee
Orcid: 0000-0002-8110-2310Affiliations:
- SK Hynix Inc., Icheon, South Korea
- Korea University, Department of Electrical Engineering, Seoul, South Korea (PhD 2019)
According to our database1,
Yeonho Lee
authored at least 14 papers
between 2016 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
IEEE J. Solid State Circuits, 2023
2022
A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector.
IEEE Access, 2021
2019
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces.
IEEE J. Solid State Circuits, 2019
A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A Spread Spectrum Clock Generator With Nested Modulation Profile for a High-Resolution Display System.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers.
IEEE Trans. Very Large Scale Integr. Syst., 2016