Yeong-Taek Lee
According to our database1,
Yeong-Taek Lee
authored at least 6 papers
between 2001 and 2012.
Collaborative distances:
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Bibliography
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2010
A 31 ns Random Cycle VCAT-Based 4F <sup>2</sup> DRAM With Manufacturability and Enhanced Cell Efficiency.
IEEE J. Solid State Circuits, 2010
2009
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure.
IEEE J. Solid State Circuits, 2009
2008
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories.
IEEE J. Solid State Circuits, 2008
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2001
A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes.
IEEE J. Solid State Circuits, 2001