Yeong-Kang Lai
According to our database1,
Yeong-Kang Lai
authored at least 60 papers
between 1996 and 2024.
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Bibliography
2024
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
2023
Proceedings of the IEEE International Conference on Consumer Electronics, 2023
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023
2022
Proceedings of the IEEE International Conference on Consumer Electronics, 2022
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022
2021
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021
2020
The Influence Measures of Light Intensity on Machine Learning for Semantic Segmentation.
Proceedings of the International SoC Design Conference, 2020
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020
2019
Proceedings of the IEEE International Conference on Consumer Electronics, 2019
Fast Motion Estimation Based on Diamond Refinement Search for High Efficiency Video Coding.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019
2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
Vehicle detection for forward collision warning system based on a cascade classifier using adaboost algorithm.
Proceedings of the 7th IEEE International Conference on Consumer Electronics - Berlin, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Conference on Consumer Electronics, 2016
Proceedings of the IEEE International Conference on Consumer Electronics, 2016
Cost-effective raster operation with enhanced shared-edge sampling for 3D graphics gaming applications.
Proceedings of the IEEE International Conference on Consumer Electronics, 2016
2015
An efficient and high quality rasterization algorithm and architecture in 3D graphics systems.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015
2014
Advanced VLSI Design Methodologies for Emerging Industrial Multimedia and Communication Applications.
VLSI Design, 2014
Proceedings of the IEEE International Conference on Consumer Electronics, 2014
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2014
2013
3-D graphics processor unit with cost-effective rasterization using valid screen space region.
IEEE Trans. Consumer Electron., 2013
Proceedings of the IEEE International Symposium on Consumer Electronics, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the IEEE International Conference on Consumer Electronics, 2013
Proceedings of the IEEE International Conference on Consumer Electronics, 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Wide color-gamut improvement with skin protection using content-based analysis for display systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2012
Algorithm and architecture design of sorting-based motion estimation algorithm for wireless video applications.
Proceedings of the IEEE International Conference on Consumer Electronics, 2012
An effective hybrid depth-perception algorithm for 2D-to-3D conversion in 3D display systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2012
2011
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011
2010
IEEE Trans. Consumer Electron., 2010
Hybrid parallel motion estimation architecture based on fast top-winners search algorithm.
IEEE Trans. Consumer Electron., 2010
A memory interleaving and interlacing architecture for deblocking filter in H.264/AVC.
IEEE Trans. Consumer Electron., 2010
2009
A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform.
IEEE Trans. Consumer Electron., 2009
Hardware Efficient Coarse-to-fine Fast Algorithm for H.264/AVC Variable Block Size Motion Estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the IEEE International Conference on Acoustics, 2009
2008
A high-speed 2-D transform architecture with unique kernel for multi-standard video applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Hybrid parallel motion estimation architecture based on fast Pel-subsampling algorithm.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008
Analysis and architecture design of multi-transform architecture for H.264/AVC intra frame coder.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008
2006
A Cost Effective Interconnection Network for Reconfigurable Computing Processor in Digital Signal Processing Applications.
IEICE Trans. Electron., 2006
Analysis and Architecture Design for Memory Efficient Parallel Embedded Block Coding Architecture in JPEG 2000.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
2005
A two-way SIMD-based reconfigurable computing architecture for multimedia applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Memory analysis and throughput enhancement for cost effective bit-plane coder in JPEG2000 applications.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
2004
A novel memoryless AES cipher architecture for networking applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A performance-driven configurable motion estimator for full-search block-matching algorithm.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
VLSI architecture of the reconfigurable computing engine for digital signal processing applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A high data-reuse architecture with double-slice processing for full-search block-matching algorithm.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2001
IEEE Trans. Consumer Electron., 2001
VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1998
A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm.
IEEE Trans. Circuits Syst. Video Technol., 1998
1997
A Flexible High-Throughput VLSI Architecture with 2-D Data-Reuse for Full-Search Motion Estimation.
Proceedings of the Proceedings 1997 International Conference on Image Processing, 1997
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997
1996
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996