Yeong-Jar Chang

According to our database, Yeong-Jar Chang authored at least 15 papers between 1994 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC.

Jai-Ming Lin, Wei-Yi Chang, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu

IEEE Trans. Very Large Scale Integr. Syst., 2021

Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation.

Jai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu

IEEE Trans. Very Large Scale Integr. Syst., 2021

2019

Intelligent Policy Selection for GPU Warp Scheduler.

Lih-Yih Chiou, Tsung-Han Yang, Jian-Tang Syu, Che-Pin Chang, Yeong-Jar Chang

Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018

Fast Steady-State Thermal Analysis.

Lih-Yih Chiou, Chun-Hao Chang, Liang-Ying Lu, Wei-Hsuan Yang, Yeong-Jar Chang, Juin-Ming Lu

Proceedings of the International SoC Design Conference, 2018

A fast thermal-aware fixed-outline floorplanning methodology based on analytical models.

Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu

Proceedings of the International Conference on Computer-Aided Design, 2018

2010

Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers.

Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process.

Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.

Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances.

Chung-Fu Lin, Chia-Fu Huang, De-Chung Lu, Chih-Chiang Hsu, Wen-Tsung Chiu, Yu-Wei Chen, Yeong-Jar Chang

Proceedings of the 2008 IEEE International Test Conference, 2008

2005

Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle.

Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.

Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

MRAM Defect Analysis and Fault Modeli.

Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Fail Pattern Identification for Memory Built-In Self-Repair.

Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2000

A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier.

Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su

J. Inf. Sci. Eng., 2000

1994

Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic.

Yeong-Jar Chang, Chung-Len Lee

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994