Yenai Ma
Orcid: 0000-0002-6156-4999
According to our database1,
Yenai Ma
authored at least 10 papers
between 2015 and 2021.
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Bibliography
2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
HALCONE : A Hardware-Level Timestamp-based Cache Coherence Scheme for Multi-GPU systems.
CoRR, 2020
2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2016
UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs.
ACM Trans. Archit. Code Optim., 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015