Yen-Po Chen
According to our database1,
Yen-Po Chen
authored at least 16 papers
between 2012 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Performance Management Decision-Making Model: Case Study on Foreign Language Learning Curriculums.
Inf., August, 2024
2018
Operator assignment with cell loading and product sequencing in labour-intensive assembly cells - a case study of a bicycle assembly company.
Int. J. Prod. Res., 2018
2017
11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2015
IEEE J. Solid State Circuits, 2015
FOCUS: Key building blocks and integration strategy of a miniaturized wireless sensor node.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails.
IEEE J. Solid State Circuits, 2014
A 266nW multi-chopper amplifier with 1.38 noise efficiency factor for neural signal recording.
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Parallelization techniques for implementing trellis algorithms on graphics processors.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Proceedings of the Symposium on VLSI Circuits, 2012
A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012