Yen-Long Lee

According to our database, Yen-Long Lee authored at least 6 papers between 2014 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs.

Yen-Long Lee, Yu-Po Cheng, Soon-Jyh Chang, Hsin-Wen Ting

IEEE Des. Test, 2018

2017

An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits.

Yen-Long Lee, Soon-Jyh Chang, Yen-Chi Chen, Yu-Po Cheng

IEEE Trans. Circuits Syst. II Express Briefs, 2017

A quick jitter tolerance estimation technique for bang-bang CDRs.

Yen-Long Lee, Soon-Jyh Chang

Proceedings of the International Test Conference in Asia, 2017

A low power duobinary voltage mode transmitter.

Ming-Hung Chien, Yen-Long Lee, Jih Ren Goh, Soon-Jyh Chang

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2015

A dual-edge sampling CES delay-locked loop based clock and data recovery circuits.

Jih Ren Goh, Yen-Long Lee, Soon-Jyh Chang

Proceedings of the VLSI Design, Automation and Test, 2015

2014

An area- and power-efficient half-rate clock and data recovery circuit.

Yen-Long Lee, Soon-Jyh Chang, Rong-Sing Chu, Yen-Chi Chen, Jih Ren Goh, Chung-Ming Huang

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014