Yen-Jen Chang
Orcid: 0000-0002-0314-6625
According to our database1,
Yen-Jen Chang
authored at least 42 papers
between 2002 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Multim. Tools Appl., January, 2024
Modified YOLO network model for metaphase cell detection in antinuclear antibody images.
Eng. Appl. Artif. Intell., January, 2024
Target-Aware Yield Prediction (TAYP) Model Used to Improve Agriculture Crop Productivity.
IEEE Trans. Geosci. Remote. Sens., 2024
2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment.
Comput. Electr. Eng., 2020
2019
IET Circuits Devices Syst., 2019
2017
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017
2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
ACM Trans. Design Autom. Electr. Syst., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Low-power content-addressable memory design using a double match-line (DML) architecture.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Low Power Selected Gating Frame Buffer (SGFB) Design.
Proceedings of the 2009 International Conference on Embedded Systems & Applications, 2009
A Novel High Performance Ternary CAM (TCAM) for LPM.
Proceedings of the 2009 International Conference on Embedded Systems & Applications, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004
Proceedings of the 2004 Design, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
2002
ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2002
An Efficient Two-Level Filter Scheme for Low Power Cache.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
Paged cache: an efficient partition architecture for reducing power, area and access time.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002