Yejia Di
Orcid: 0000-0002-0276-5088
According to our database1,
Yejia Di
authored at least 16 papers
between 2016 and 2020.
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Bibliography
2020
Process Variation Aware Read Performance Improvement for LDPC-Based nand Flash Memory.
IEEE Trans. Reliab., 2020
2019
Minimizing Retention Induced Refresh Through Exploiting Process Variation of Flash Memory.
IEEE Trans. Computers, 2019
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019
2018
Exploiting Chip Idleness for Minimizing Garbage Collection - Induced Chip Access Conflict on SSDs.
ACM Trans. Design Autom. Electr. Syst., 2018
Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Access Characteristic Guided Read and Write Regulation on Flash Based Storage Systems.
IEEE Trans. Computers, 2018
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Loss is Gain: Shortening Data for Lifetime Improvement on Low-Cost ECC Enabled Consumer-Level Flash Memory.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Revisiting wear leveling design on compression applied 3D NAND flash memory: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018
2017
Improving read performance via selective Vpass reduction on high density 3D NAND flash memory.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017
Exploiting Process Variation for Read Performance Improvement on LDPC Based Flash Memory Storage Systems.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
A PV aware data placement scheme for read performance improvement on LDPC based flash memory: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
2016
Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Minimizing cell-to-cell interference by exploiting differential bit impact characteristics of scaled MLC NAND flash memories.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016
Exploiting process variation for retention induced refresh minimization on flash memory.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016