Yehuda Kra

Orcid: 0009-0002-3377-6529

According to our database1, Yehuda Kra authored at least 10 papers between 1993 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

Basecalling by Statistical Profiling and Hardware-Accelerated Convolutional Neural Network.
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024

Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2022
Silicon-Proven Clockless Wave-Propagated Pipelining for High-Throughput, Energy-Efficient Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A RISC-V-based Research Platform for Rapid Design Cycle.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2021
WP 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated Pipelining.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Physically Aware Affinity-Driven Multiplier Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

1993
A Cross-Debugging Method for Hardware/Software Co-design Environments.
Proceedings of the 30th Design Automation Conference. Dallas, 1993


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