Yeh-Ning Jou

According to our database¹, Yeh-Ning Jou authored at least 9 papers between 2008 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2024

Negative Triggering Current Induced the Latch-up in the Circuit without the ESD device to Power.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024

2023

Transmission Line Pulse Width Impacting on Device Performances.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

Bipolar Transistors' Holding Phenomena.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

2022

Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2022

Gate Voltages Impacting on Latch-up Measurements.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022

2019

Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

2015

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2015

2009

Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Yeh-Ning Jou

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Bibliography

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